From 7ff0c89d51cce9ade35f1f7ca602e226da8922aa Mon Sep 17 00:00:00 2001
From: Robert Jordens <rj@m-labs.hk>
Date: Fri, 4 Mar 2016 00:03:48 +0100
Subject: [PATCH] kc705.clock: add all spi buses

---
 artiq/gateware/targets/kc705.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
index 778cdc68d..16ad41bf8 100755
--- a/artiq/gateware/targets/kc705.py
+++ b/artiq/gateware/targets/kc705.py
@@ -264,7 +264,7 @@ class NIST_CLOCK(_NIST_Ions):
         rtio_channels.append(rtio.Channel.from_phy(
             phy, ofifo_depth=4, ififo_depth=4))
 
-        for i in range(1):  # spi1 and spi2 collide in pinout with ttl
+        for i in range(3):
             phy = spi.SPIMaster(self.platform.request("spi", i))
             self.submodules += phy
             rtio_channels.append(rtio.Channel.from_phy(