forked from M-Labs/artiq
drtio: aux controller unittest WIP
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import unittest
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from types import SimpleNamespace
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from migen import *
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from artiq.gateware.drtio.link_layer import *
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from artiq.gateware.drtio.aux_controller import *
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class Loopback(Module):
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def __init__(self, nwords):
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ks = [Signal() for k in range(nwords)]
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ds = [Signal(8) for d in range(nwords)]
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encoder = SimpleNamespace(k=ks, d=ds)
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decoders = [SimpleNamespace(k=k, d=d) for k, d in zip(ks, ds)]
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self.submodules.tx = LinkLayerTX(encoder)
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self.submodules.rx = LinkLayerRX(decoders)
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self.ready = Signal()
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self.tx_aux_frame = self.tx.aux_frame
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self.tx_aux_data = self.tx.aux_data
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self.tx_aux_ack = self.tx.aux_ack
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self.tx_rt_frame = self.tx.rt_frame
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self.tx_rt_data = self.tx.rt_data
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self.rx_aux_stb = self.rx.aux_stb
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self.rx_aux_frame = self.rx.aux_frame & self.ready
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self.rx_aux_data = self.rx.aux_data
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self.rx_rt_frame = self.rx.rt_frame & self.ready
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self.rx_rt_data = self.rx.rt_data
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class TB(Module):
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def __init__(self, nwords):
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self.submodules.link_layer = Loopback(nwords)
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self.submodules.aux_controller = ClockDomainsRenamer(
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{"rtio": "sys", "rtio_rx": "sys"})(AuxController(self.link_layer))
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class TestAuxController(unittest.TestCase):
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def test_aux_controller(self):
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dut = TB(4)
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def gen():
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yield dut.link_layer.tx.link_init.eq(1)
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yield
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yield
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yield dut.link_layer.tx.link_init.eq(0)
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while not (yield dut.link_layer.rx.link_init):
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yield
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while (yield dut.link_layer.rx.link_init):
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yield
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yield dut.link_layer.ready.eq(1)
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yield
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yield from dut.aux_controller.bus.write(0, 0x42)
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yield from dut.aux_controller.bus.write(1, 0x23)
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yield from dut.aux_controller.transmitter.aux_tx_length.write(8)
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yield from dut.aux_controller.transmitter.aux_tx.write(1)
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for i in range(40):
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yield
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print(hex((yield from dut.aux_controller.bus.read(256))))
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print(hex((yield from dut.aux_controller.bus.read(257))))
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print((yield from dut.aux_controller.receiver.aux_rx_length.read()))
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run_simulation(dut, gen(), vcd_name="foo.vcd")
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