forked from M-Labs/artiq
drtio: aux controller fixes
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e1394db861
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6c9965b444
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@ -12,11 +12,12 @@ max_packet = 1024
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class Transmitter(Module, AutoCSR):
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def __init__(self, link_layer, min_mem_dw):
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self.aux_tx_length = CSRStorage(bits_for(max_packet))
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self.aux_tx = CSR()
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ll_dw = len(link_layer.tx_aux_data)
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mem_dw = max(min_mem_dw, ll_dw)
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self.aux_tx_length = CSRStorage(bits_for(max_packet),
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alignment_bits=log2_int(mem_dw//8))
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self.aux_tx = CSR()
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self.specials.mem = Memory(mem_dw, max_packet//(mem_dw//8))
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converter = stream.Converter(mem_dw, ll_dw)
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@ -83,7 +84,9 @@ class Transmitter(Module, AutoCSR):
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)
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fsm.act("TRANSMIT",
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converter.sink.stb.eq(1),
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frame_counter_ce.eq(1),
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If(converter.sink.ack,
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frame_counter_ce.eq(1)
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),
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If(frame_counter_next == tx_length, NextState("WAIT_INTERFRAME"))
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)
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fsm.act("WAIT_INTERFRAME",
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@ -109,7 +112,7 @@ class Receiver(Module, AutoCSR):
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# when continuously drained, the Converter accepts data continuously
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self.sync.rtio_rx += [
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converter.sink.stb.eq(link_layer.rx_aux_stb),
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converter.sink.stb.eq(link_layer.rx_aux_stb & link_layer.rx_aux_frame),
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converter.sink.data.eq(link_layer.rx_aux_data)
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]
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self.comb += converter.sink.eop.eq(link_layer.rx_aux_stb & ~link_layer.rx_aux_frame)
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@ -145,7 +148,7 @@ class Receiver(Module, AutoCSR):
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fsm = ClockDomainsRenamer("rtio_rx")(FSM(reset_state="IDLE"))
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self.submodules += fsm
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sop = Signal()
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sop = Signal(reset=1)
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self.sync.rtio_rx += \
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If(converter.source.stb,
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If(converter.source.eop,
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