forked from M-Labs/artiq
drtio: more fixes and tests
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22173b8c70
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@ -37,7 +37,7 @@ class RTController(Module):
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def __init__(self, rt_packets, channel_count, fine_ts_width):
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self.kcsrs = _KernelCSRs()
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self.submodules.counter = RTIOCounter(64)
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self.submodules.counter = RTIOCounter(64-fine_ts_width)
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self.sync += If(self.kcsrs.counter_update.re,
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self.kcsrs.counter.status.eq(self.counter.value_sys))
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tsc_correction = Signal(64)
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@ -93,10 +93,10 @@ class RTController(Module):
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# TODO: collision, replace, busy
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cond_sequence_error = self.kcsrs.o_timestamp.storage < last_timestamps.dat_r
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cond_underflow = ((self.kcsrs.o_timestamp.storage - self.kcsrs.underflow_margin.storage
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>> fine_ts_width) < self.counter.value_sys)
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cond_fifo_emptied = ((last_timestamps.dat_r
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< self.counter.value_sys - self.kcsrs.underflow_margin.storage)
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cond_underflow = ((self.kcsrs.o_timestamp.storage[fine_ts_width:]
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- self.kcsrs.underflow_margin.storage[fine_ts_width:]) < self.counter.value_sys)
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cond_fifo_emptied = ((last_timestamps.dat_r[fine_ts_width:]
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< self.counter.value_sys - self.kcsrs.underflow_margin.storage[fine_ts_width:])
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& (last_timestamps.dat_r != 0))
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fsm.act("IDLE",
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@ -124,7 +124,7 @@ class RTController(Module):
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fifo_spaces.dat_w.eq(fifo_spaces.dat_r - 1)
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),
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last_timestamps.we.eq(1),
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If(fifo_spaces.dat_r <= 1,
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If(~cond_fifo_emptied & (fifo_spaces.dat_r <= 1),
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NextState("GET_FIFO_SPACE")
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).Else(
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NextState("IDLE")
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@ -47,8 +47,8 @@ class DUT(Module):
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self.submodules.phy0 = ttl_simple.Output(self.ttl0)
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self.submodules.phy1 = ttl_simple.Output(self.ttl1)
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rtio_channels = [
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rtio.Channel.from_phy(self.phy0),
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rtio.Channel.from_phy(self.phy1)
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rtio.Channel.from_phy(self.phy0, ofifo_depth=4),
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rtio.Channel.from_phy(self.phy1, ofifo_depth=4)
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]
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self.submodules.satellite = DRTIOSatellite(
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self.transceivers.bob, rx_synchronizer, rtio_channels)
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@ -79,6 +79,7 @@ class TestFullStack(unittest.TestCase):
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yield from kcsrs.o_we.write(1)
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yield
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status = 1
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wlen = 0
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while status:
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status = yield from kcsrs.o_status.read()
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if status & 2:
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@ -88,6 +89,8 @@ class TestFullStack(unittest.TestCase):
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yield from kcsrs.o_sequence_error_reset.write(1)
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raise RTIOSequenceError
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yield
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wlen += 1
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return wlen
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def test():
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yield from get_fifo_space(0)
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@ -109,9 +112,28 @@ class TestFullStack(unittest.TestCase):
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yield from write(0, 1)
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delay(200*8)
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for _ in range(50):
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delay(200*8)
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max_wlen = 0
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for _ in range(3):
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wlen = yield from write(0, 1)
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max_wlen = max(max_wlen, wlen)
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delay(40*8)
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wlen = yield from write(0, 0)
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max_wlen = max(max_wlen, wlen)
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delay(40*8)
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# check that some writes caused FIFO space requests
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self.assertGreater(max_wlen, 5)
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# wait for all TTL events to execute
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for _ in range(40):
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yield
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# check "last timestamp passed" FIFO empty condition
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delay(1000*8)
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wlen = yield from write(0, 1)
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self.assertEqual(wlen, 2)
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ttl_changes = []
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@passive
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def check_ttls():
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@ -128,10 +150,17 @@ class TestFullStack(unittest.TestCase):
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run_simulation(dut,
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{"sys": test(), "rtio": check_ttls()},
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{"sys": 8, "rtio": 5, "rtio_rx": 5, "rio": 5, "rio_phy": 5}, vcd_name="foo.vcd")
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{"sys": 8, "rtio": 5, "rtio_rx": 5, "rio": 5, "rio_phy": 5})
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self.assertEqual(ttl_changes, [
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(203, 0),
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(208, 0),
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(208, 1),
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(214, 1)
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(214, 1),
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(414, 0),
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(454, 0),
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(494, 0),
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(534, 0),
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(574, 0),
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(614, 0)
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])
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