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firmware: bypass channel divider for HMC7043 DCLK

This commit is contained in:
Sebastien Bourdeauducq 2019-01-27 11:49:34 +08:00
parent f73ffe44f9
commit 7e5c062c2c
1 changed files with 3 additions and 2 deletions
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5
artiq/firmware/libboard_artiq/hmc830_7043.rs
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@ -159,8 +159,9 @@ pub mod hmc7043 {
use board_misoc::{csr, clock}; use board_misoc::{csr, clock};
// Warning: dividers are not synchronized with HMC830 clock input! // Warning: dividers are not synchronized with HMC830 clock input!
// Set DAC_CLK_DIV to 1 for deterministic phase. // Set DAC_CLK_DIV to 1 or 0 for deterministic phase.
pub const DAC_CLK_DIV: u16 = 1; // 2400MHz // (0 bypasses the divider and reduces noise)
pub const DAC_CLK_DIV: u16 = 0; // 2400MHz
pub const FPGA_CLK_DIV: u16 = 16; // 150MHz pub const FPGA_CLK_DIV: u16 = 16; // 150MHz
pub const SYSREF_DIV: u16 = 256; // 9.375MHz pub const SYSREF_DIV: u16 = 256; // 9.375MHz
const HMC_SYSREF_DIV: u16 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz) const HMC_SYSREF_DIV: u16 = SYSREF_DIV*8; // 1.171875MHz (must be <= 4MHz)