From 7d9c7ada713bbf60cce8665b4892dcd7532f0bd6 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 20 Feb 2018 17:42:00 +0800
Subject: [PATCH] drtio: fix test infinite loop

---
 artiq/gateware/test/drtio/test_full_stack.py | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/artiq/gateware/test/drtio/test_full_stack.py b/artiq/gateware/test/drtio/test_full_stack.py
index 23810321c..905d188d5 100644
--- a/artiq/gateware/test/drtio/test_full_stack.py
+++ b/artiq/gateware/test/drtio/test_full_stack.py
@@ -68,6 +68,10 @@ class DUT(Module):
         self.submodules.satellite = DRTIOSatellite(
             self.transceivers.bob, rtio_channels, rx_synchronizer,
             lane_count=4, fifo_depth=8, fine_ts_width=0)
+        self.satellite.reset.storage.reset = 0
+        self.satellite.reset.storage_full.reset = 0
+        self.satellite.reset_phy.storage.reset = 0
+        self.satellite.reset_phy.storage_full.reset = 0
 
 
 class OutputsTestbench: