forked from M-Labs/artiq
gateware/serwb: generate wishbone error on wishbone slave when access while link is not ready
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89558e2653
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@ -645,6 +645,7 @@ class EtherboneWishboneMaster(Module):
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class EtherboneWishboneSlave(Module):
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def __init__(self):
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self.bus = bus = wishbone.Interface()
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self.ready = Signal(reset=1)
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self.sink = sink = stream.Endpoint(etherbone_mmap_description(32))
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self.source = source = stream.Endpoint(etherbone_mmap_description(32))
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@ -654,10 +655,14 @@ class EtherboneWishboneSlave(Module):
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fsm.act("IDLE",
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sink.ack.eq(1),
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If(bus.stb & bus.cyc,
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If(bus.we,
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NextState("SEND_WRITE")
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If(self.ready,
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If(bus.we,
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NextState("SEND_WRITE")
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).Else(
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NextState("SEND_READ")
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)
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).Else(
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NextState("SEND_READ")
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NextState("SEND_ERROR")
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)
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)
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)
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@ -694,7 +699,10 @@ class EtherboneWishboneSlave(Module):
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NextState("IDLE")
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)
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)
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fsm.act("SEND_ERROR",
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bus.ack.eq(1),
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bus.err.eq(1)
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)
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# etherbone
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@ -86,6 +86,7 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
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self.submodules += serwb_depacketizer, serwb_packetizer
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serwb_etherbone = serwb.etherbone.Etherbone(mode="slave")
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self.submodules += serwb_etherbone
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self.comb += serwb_etherbone.wishbone.ready.eq(serwb_init.ready)
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serwb_tx_cdc = ClockDomainsRenamer({"write": "sys", "read": "serdes"})(
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stream.AsyncFIFO([("data", 32)], 8))
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self.submodules += serwb_tx_cdc
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