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targets: avoid passing cpu_type around unnecessarily

This commit is contained in:
Sebastien Bourdeauducq 2018-01-11 11:21:55 +08:00
parent 6d58c4390b
commit 7c82fcf41a
4 changed files with 14 additions and 14 deletions
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8
artiq/gateware/targets/kasli.py
View File

@ -80,9 +80,9 @@ class _KasliBase(MiniSoC, AMPSoC):
} }
mem_map.update(MiniSoC.mem_map) mem_map.update(MiniSoC.mem_map)
def __init__(self, cpu_type="or1k", **kwargs): def __init__(self, **kwargs):
MiniSoC.__init__(self, MiniSoC.__init__(self,
cpu_type=cpu_type, cpu_type="or1k",
sdram_controller_type="minicon", sdram_controller_type="minicon",
l2_size=128*1024, l2_size=128*1024,
ident=artiq_version, ident=artiq_version,
@ -147,8 +147,8 @@ class Opticlock(_KasliBase):
""" """
Opticlock extension configuration Opticlock extension configuration
""" """
def __init__(self, cpu_type="or1k", **kwargs): def __init__(self, **kwargs):
_KasliBase.__init__(self, cpu_type, **kwargs) _KasliBase.__init__(self, **kwargs)
platform = self.platform platform = self.platform
platform.add_extension(_dio("eem0")) platform.add_extension(_dio("eem0"))

12
artiq/gateware/targets/kc705_dds.py
View File

@ -210,9 +210,9 @@ class _NIST_Ions(MiniSoC, AMPSoC):
} }
mem_map.update(MiniSoC.mem_map) mem_map.update(MiniSoC.mem_map)
def __init__(self, cpu_type="or1k", **kwargs): def __init__(self, **kwargs):
MiniSoC.__init__(self, MiniSoC.__init__(self,
cpu_type=cpu_type, cpu_type="or1k",
sdram_controller_type="minicon", sdram_controller_type="minicon",
l2_size=128*1024, l2_size=128*1024,
ident=artiq_version, ident=artiq_version,
@ -277,8 +277,8 @@ class NIST_CLOCK(_NIST_Ions):
""" """
NIST clock hardware, with old backplane and 11 DDS channels NIST clock hardware, with old backplane and 11 DDS channels
""" """
def __init__(self, cpu_type="or1k", **kwargs): def __init__(self, **kwargs):
_NIST_Ions.__init__(self, cpu_type, **kwargs) _NIST_Ions.__init__(self, **kwargs)
platform = self.platform platform = self.platform
platform.add_extension(nist_clock.fmc_adapter_io) platform.add_extension(nist_clock.fmc_adapter_io)
@ -379,8 +379,8 @@ class NIST_QC2(_NIST_Ions):
NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
and 24 DDS channels. Two backplanes are used. and 24 DDS channels. Two backplanes are used.
""" """
def __init__(self, cpu_type="or1k", **kwargs): def __init__(self, **kwargs):
_NIST_Ions.__init__(self, cpu_type, **kwargs) _NIST_Ions.__init__(self, **kwargs)
platform = self.platform platform = self.platform
platform.add_extension(nist_qc2.fmc_adapter_io) platform.add_extension(nist_qc2.fmc_adapter_io)

4
artiq/gateware/targets/kc705_sma_spi.py
View File

@ -81,8 +81,8 @@ class SMA_SPI(_NIST_Ions):
""" """
SPI on 4 SMA for PDQ2 test/demo. SPI on 4 SMA for PDQ2 test/demo.
""" """
def __init__(self, cpu_type="or1k", **kwargs): def __init__(self, **kwargs):
_NIST_Ions.__init__(self, cpu_type, **kwargs) _NIST_Ions.__init__(self, **kwargs)
platform = self.platform platform = self.platform
self.platform.add_extension(_sma_spi) self.platform.add_extension(_sma_spi)

4
artiq/gateware/targets/sayma_amc_standalone.py
View File

@ -122,9 +122,9 @@ class Standalone(MiniSoC, AMPSoC):
} }
mem_map.update(MiniSoC.mem_map) mem_map.update(MiniSoC.mem_map)
def __init__(self, cpu_type="or1k", with_sawg=False, **kwargs): def __init__(self, with_sawg=False, **kwargs):
MiniSoC.__init__(self, MiniSoC.__init__(self,
cpu_type=cpu_type, cpu_type="or1k",
sdram_controller_type="minicon", sdram_controller_type="minicon",
l2_size=128*1024, l2_size=128*1024,
ident=artiq_version, ident=artiq_version,