diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py
index c4c90561d..0e0346c12 100644
--- a/artiq/gateware/targets/kasli.py
+++ b/artiq/gateware/targets/kasli.py
@@ -80,9 +80,9 @@ class _KasliBase(MiniSoC, AMPSoC):
     }
     mem_map.update(MiniSoC.mem_map)
 
-    def __init__(self, cpu_type="or1k", **kwargs):
+    def __init__(self, **kwargs):
         MiniSoC.__init__(self,
-                         cpu_type=cpu_type,
+                         cpu_type="or1k",
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
                          ident=artiq_version,
@@ -147,8 +147,8 @@ class Opticlock(_KasliBase):
     """
     Opticlock extension configuration
     """
-    def __init__(self, cpu_type="or1k", **kwargs):
-        _KasliBase.__init__(self, cpu_type, **kwargs)
+    def __init__(self, **kwargs):
+        _KasliBase.__init__(self, **kwargs)
 
         platform = self.platform
         platform.add_extension(_dio("eem0"))
diff --git a/artiq/gateware/targets/kc705_dds.py b/artiq/gateware/targets/kc705_dds.py
index bb6a662eb..31baed85e 100755
--- a/artiq/gateware/targets/kc705_dds.py
+++ b/artiq/gateware/targets/kc705_dds.py
@@ -210,9 +210,9 @@ class _NIST_Ions(MiniSoC, AMPSoC):
     }
     mem_map.update(MiniSoC.mem_map)
 
-    def __init__(self, cpu_type="or1k", **kwargs):
+    def __init__(self, **kwargs):
         MiniSoC.__init__(self,
-                         cpu_type=cpu_type,
+                         cpu_type="or1k",
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
                          ident=artiq_version,
@@ -277,8 +277,8 @@ class NIST_CLOCK(_NIST_Ions):
     """
     NIST clock hardware, with old backplane and 11 DDS channels
     """
-    def __init__(self, cpu_type="or1k", **kwargs):
-        _NIST_Ions.__init__(self, cpu_type, **kwargs)
+    def __init__(self, **kwargs):
+        _NIST_Ions.__init__(self, **kwargs)
 
         platform = self.platform
         platform.add_extension(nist_clock.fmc_adapter_io)
@@ -379,8 +379,8 @@ class NIST_QC2(_NIST_Ions):
     NIST QC2 hardware, as used in Quantum I and Quantum II, with new backplane
     and 24 DDS channels.  Two backplanes are used.
     """
-    def __init__(self, cpu_type="or1k", **kwargs):
-        _NIST_Ions.__init__(self, cpu_type, **kwargs)
+    def __init__(self, **kwargs):
+        _NIST_Ions.__init__(self, **kwargs)
 
         platform = self.platform
         platform.add_extension(nist_qc2.fmc_adapter_io)
diff --git a/artiq/gateware/targets/kc705_sma_spi.py b/artiq/gateware/targets/kc705_sma_spi.py
index 63f91a3a5..cd1a705e5 100755
--- a/artiq/gateware/targets/kc705_sma_spi.py
+++ b/artiq/gateware/targets/kc705_sma_spi.py
@@ -81,8 +81,8 @@ class SMA_SPI(_NIST_Ions):
     """
     SPI on 4 SMA for PDQ2 test/demo.
     """
-    def __init__(self, cpu_type="or1k", **kwargs):
-        _NIST_Ions.__init__(self, cpu_type, **kwargs)
+    def __init__(self, **kwargs):
+        _NIST_Ions.__init__(self, **kwargs)
 
         platform = self.platform
         self.platform.add_extension(_sma_spi)
diff --git a/artiq/gateware/targets/sayma_amc_standalone.py b/artiq/gateware/targets/sayma_amc_standalone.py
index 82fcfdc51..7c8429175 100755
--- a/artiq/gateware/targets/sayma_amc_standalone.py
+++ b/artiq/gateware/targets/sayma_amc_standalone.py
@@ -122,9 +122,9 @@ class Standalone(MiniSoC, AMPSoC):
     }
     mem_map.update(MiniSoC.mem_map)
 
-    def __init__(self, cpu_type="or1k", with_sawg=False, **kwargs):
+    def __init__(self, with_sawg=False, **kwargs):
         MiniSoC.__init__(self,
-                         cpu_type=cpu_type,
+                         cpu_type="or1k",
                          sdram_controller_type="minicon",
                          l2_size=128*1024,
                          ident=artiq_version,