firmware: add routing table (WIP)

artiq/firmware/libboard_artiq/drtio_routing.rs

@@ -0,0 +1,59 @@
+use board_misoc::{csr, config};
+
+pub const DEST_COUNT: usize = 256;
+pub const MAX_HOPS: usize = 32;
+pub const INVALID_HOP: u8 = 0xff;
+
+pub struct RoutingTable([[u8; MAX_HOPS]; DEST_COUNT]);
+
+impl RoutingTable {
+    // default routing table is for star topology with no hops
+    fn default_master() -> RoutingTable {
+        let mut ret = RoutingTable([[INVALID_HOP; MAX_HOPS]; DEST_COUNT]);
+        for i in 0..csr::DRTIO.len() {
+            ret.0[i][0] = i as u8;
+        }
+        for i in 1..csr::DRTIO.len() {
+            ret.0[i][1] = 0x00;
+        }
+        ret
+    }
+
+    // satellites receive the routing table from the master
+    // by default, block everything
+    fn default_satellite() -> RoutingTable {
+        RoutingTable([[INVALID_HOP; MAX_HOPS]; DEST_COUNT])
+    }
+}
+
+pub fn config_routing_table() -> RoutingTable {
+    let mut ret = RoutingTable::default_master();
+    let ok = config::read("routing_table", |result| {
+        if let Ok(data) = result {
+            if data.len() == DEST_COUNT*MAX_HOPS {
+                for i in 0..DEST_COUNT {
+                    for j in 0..MAX_HOPS {
+                        ret.0[i][j] = data[i*MAX_HOPS+j];
+                    }
+                }
+                return true;
+            }
+        }
+        false
+    });
+    if !ok {
+        warn!("could not read routing table from configuration, using default");
+    } 
+    ret
+}
+
+pub fn program_interconnect(rt: &RoutingTable, rank: u8)
+{
+    for i in 0..DEST_COUNT {
+        let hop = rt.0[i][rank as usize];
+        unsafe {
+            csr::cri_con::routing_destination_write(i as _);
+            csr::cri_con::routing_hop_write(hop);
+        }
+    }
+}

artiq/firmware/libboard_artiq/lib.rs

@@ -48,3 +48,5 @@ pub mod grabber;
 
 #[cfg(has_drtio)]
 pub mod drtioaux;
+#[cfg(has_drtio_routing)]
+pub mod drtio_routing;

artiq/frontend/artiq_route.py

@@ -26,19 +26,19 @@ def get_argparser():
     return parser
 
 
-ENTRY_COUNT = 256
+DEST_COUNT = 256
 MAX_HOPS = 32
 
 
 def init(filename):
     with open(filename, "wb") as f:
-        f.write(b"\xff"*(ENTRY_COUNT*MAX_HOPS))
+        f.write(b"\xff"*(DEST_COUNT*MAX_HOPS))
 
 
 def show_routes(filename):
     routes = []
     with open(filename, "rb") as f:
-        for i in range(ENTRY_COUNT):
+        for i in range(DEST_COUNT):
             hops = [int.from_bytes(f.read(1), "big") for j in range(MAX_HOPS)]
             routes.append(hops)
 
@@ -54,8 +54,8 @@ def show_routes(filename):
 
 def set_route(filename, destination, hops):
     with open(filename, "r+b") as f:
-        if destination >= ENTRY_COUNT:
+        if destination >= DEST_COUNT:
-            raise ValueError("destination must be less than {}".format(ENTRY_COUNT))
+            raise ValueError("destination must be less than {}".format(DEST_COUNT))
         f.seek(destination*MAX_HOPS)
 
         if len(hops) + 1 >= MAX_HOPS:

artiq/gateware/targets/kasli.py

@@ -854,9 +854,9 @@ class _SatelliteBase(BaseSoC):
                               coreaux.bus)
             self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
         self.config["HAS_DRTIO"] = None
+        self.config["HAS_DRTIO_ROUTING"] = None
         self.add_csr_group("drtioaux", drtioaux_csr_group)
         self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
-        self.config["HAS_DRTIOREP"] = None
         self.add_csr_group("drtiorep", drtiorep_csr_group)
 
         self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)