forked from M-Labs/artiq
kasli: enable routing in Master
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ec302747e0
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496d1b08fd
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@ -693,6 +693,7 @@ class _MasterBase(MiniSoC, AMPSoC):
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtio", drtio_csr_group)
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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@ -726,7 +727,8 @@ class _MasterBase(MiniSoC, AMPSoC):
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self.register_kernel_cpu_csrdevice("rtio_dma")
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self.submodules.cri_con = rtio.CRIInterconnectShared(
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[self.rtio.cri, self.rtio_dma.cri],
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[self.rtio_core.cri] + self.drtio_cri)
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[self.rtio_core.cri] + self.drtio_cri,
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enable_routing=True)
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self.register_kernel_cpu_csrdevice("cri_con")
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self.submodules.rtio_analyzer = rtio.Analyzer(self.rtio_tsc, self.cri_con.switch.slave,
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