forked from M-Labs/artiq
firmware: add routing table (WIP)
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496d1b08fd
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7ae44f3417
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@ -0,0 +1,59 @@
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use board_misoc::{csr, config};
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pub const DEST_COUNT: usize = 256;
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pub const MAX_HOPS: usize = 32;
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pub const INVALID_HOP: u8 = 0xff;
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pub struct RoutingTable([[u8; MAX_HOPS]; DEST_COUNT]);
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impl RoutingTable {
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// default routing table is for star topology with no hops
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fn default_master() -> RoutingTable {
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let mut ret = RoutingTable([[INVALID_HOP; MAX_HOPS]; DEST_COUNT]);
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for i in 0..csr::DRTIO.len() {
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ret.0[i][0] = i as u8;
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}
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for i in 1..csr::DRTIO.len() {
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ret.0[i][1] = 0x00;
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}
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ret
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}
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// satellites receive the routing table from the master
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// by default, block everything
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fn default_satellite() -> RoutingTable {
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RoutingTable([[INVALID_HOP; MAX_HOPS]; DEST_COUNT])
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}
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}
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pub fn config_routing_table() -> RoutingTable {
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let mut ret = RoutingTable::default_master();
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let ok = config::read("routing_table", |result| {
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if let Ok(data) = result {
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if data.len() == DEST_COUNT*MAX_HOPS {
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for i in 0..DEST_COUNT {
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for j in 0..MAX_HOPS {
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ret.0[i][j] = data[i*MAX_HOPS+j];
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}
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}
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return true;
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}
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}
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false
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});
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if !ok {
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warn!("could not read routing table from configuration, using default");
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}
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ret
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}
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pub fn program_interconnect(rt: &RoutingTable, rank: u8)
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{
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for i in 0..DEST_COUNT {
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let hop = rt.0[i][rank as usize];
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unsafe {
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csr::cri_con::routing_destination_write(i as _);
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csr::cri_con::routing_hop_write(hop);
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}
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}
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}
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@ -48,3 +48,5 @@ pub mod grabber;
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#[cfg(has_drtio)]
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pub mod drtioaux;
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#[cfg(has_drtio_routing)]
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pub mod drtio_routing;
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@ -26,19 +26,19 @@ def get_argparser():
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return parser
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ENTRY_COUNT = 256
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DEST_COUNT = 256
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MAX_HOPS = 32
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def init(filename):
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with open(filename, "wb") as f:
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f.write(b"\xff"*(ENTRY_COUNT*MAX_HOPS))
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f.write(b"\xff"*(DEST_COUNT*MAX_HOPS))
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def show_routes(filename):
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routes = []
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with open(filename, "rb") as f:
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for i in range(ENTRY_COUNT):
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for i in range(DEST_COUNT):
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hops = [int.from_bytes(f.read(1), "big") for j in range(MAX_HOPS)]
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routes.append(hops)
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@ -54,8 +54,8 @@ def show_routes(filename):
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def set_route(filename, destination, hops):
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with open(filename, "r+b") as f:
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if destination >= ENTRY_COUNT:
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raise ValueError("destination must be less than {}".format(ENTRY_COUNT))
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if destination >= DEST_COUNT:
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raise ValueError("destination must be less than {}".format(DEST_COUNT))
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f.seek(destination*MAX_HOPS)
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if len(hops) + 1 >= MAX_HOPS:
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@ -854,9 +854,9 @@ class _SatelliteBase(BaseSoC):
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coreaux.bus)
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self.add_memory_region(memory_name, memory_address | self.shadow_base, 0x800)
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self.config["HAS_DRTIO"] = None
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self.config["HAS_DRTIO_ROUTING"] = None
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self.add_csr_group("drtioaux", drtioaux_csr_group)
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self.add_memory_group("drtioaux_mem", drtioaux_memory_group)
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self.config["HAS_DRTIOREP"] = None
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self.add_csr_group("drtiorep", drtiorep_csr_group)
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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