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ddb_temp: select appropriate compiler target

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occheung 2021-11-08 13:04:48 +08:00 committed by Sébastien Bourdeauducq
parent 531670d6c5
commit 750b0ce46d
2 changed files with 14 additions and 10 deletions
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10
artiq/coredevice/core.py
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@ -11,7 +11,7 @@ from artiq.language.units import *
from artiq.compiler.module import Module from artiq.compiler.module import Module
from artiq.compiler.embedding import Stitcher from artiq.compiler.embedding import Stitcher
from artiq.compiler.targets import RISCVTarget, CortexA9Target from artiq.compiler.targets import RV32IMATarget, RV32GTarget, CortexA9Target
from artiq.coredevice.comm_kernel import CommKernel, CommKernelDummy from artiq.coredevice.comm_kernel import CommKernel, CommKernelDummy
# Import for side effects (creating the exception classes). # Import for side effects (creating the exception classes).
@ -71,11 +71,13 @@ class Core:
"core", "ref_period", "coarse_ref_period", "ref_multiplier", "core", "ref_period", "coarse_ref_period", "ref_multiplier",
} }
def __init__(self, dmgr, host, ref_period, ref_multiplier=8, target="riscv"): def __init__(self, dmgr, host, ref_period, ref_multiplier=8, target="rv32g"):
self.ref_period = ref_period self.ref_period = ref_period
self.ref_multiplier = ref_multiplier self.ref_multiplier = ref_multiplier
if target == "riscv": if target == "rv32g":
self.target_cls = RISCVTarget self.target_cls = RV32GTarget
elif target == "rv32ima":
self.target_cls = RV32IMATarget
elif target == "cortexa9": elif target == "cortexa9":
self.target_cls = CortexA9Target self.target_cls = CortexA9Target
else: else:

14
artiq/frontend/artiq_ddb_template.py
View File

@ -11,14 +11,16 @@ from artiq.coredevice import jsondesc
def process_header(output, description): def process_header(output, description):
if description["target"] not in ("kasli", "kasli_soc"): if description["target"] == "kasli":
if description["hw_rev"] in ("v1.0", "v1.1"):
cpu_target = "rv32ima"
else:
cpu_target = "rv32g"
elif description["target"] == "kasli_soc":
cpu_target = "cortexa9"
else:
raise NotImplementedError raise NotImplementedError
cpu_target = {
"kasli": "riscv",
"kasli_soc": "cortexa9"
}[description["target"]]
print(textwrap.dedent(""" print(textwrap.dedent("""
# Autogenerated for the {variant} variant # Autogenerated for the {variant} variant
core_addr = "{core_addr}" core_addr = "{core_addr}"