From 7405006668cf4dffd87b9cc9bba8af8f772c465c Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Tue, 16 Jan 2018 18:19:04 +0100 Subject: [PATCH] sayma: rtio clock is jesd fabric clock --- artiq/gateware/targets/sayma_amc_standalone.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc_standalone.py b/artiq/gateware/targets/sayma_amc_standalone.py index b84ff4d26..25ec0e506 100755 --- a/artiq/gateware/targets/sayma_amc_standalone.py +++ b/artiq/gateware/targets/sayma_amc_standalone.py @@ -220,8 +220,8 @@ class Standalone(MiniSoC, AMPSoC): self.clock_domains.cd_rtio = ClockDomain() self.comb += [ - self.cd_rtio.clk.eq(ClockSignal()), - self.cd_rtio.rst.eq(ResetSignal()) + self.cd_rtio.clk.eq(ClockSignal("jesd")), + self.cd_rtio.rst.eq(ResetSignal("jesd")) ] self.submodules.rtio_core = rtio.Core(rtio_channels) self.csr_devices.append("rtio_core")