forked from M-Labs/artiq
shuttler: add documentation
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@ -9,10 +9,27 @@ from artiq.language.units import us
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@portable
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def shuttler_volt_to_mu(volt):
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"""Return the equivalent DAC code. Valid input range is from -10 to
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10 - LSB.
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"""
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return round((1 << 14) * (volt / 20.0)) & 0x3fff
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class Config:
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"""Shuttler configuration registers interface.
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The configuration registers control waveform phase auto-clear, and pre-DAC
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gain & offset values for calibration with ADC on the Shuttler AFE card.
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To find the calibrated DAC code, the Shuttler core first multiplies the
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output data with pre-DAC gain, then adds the offset.
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.. note::
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The DAC code is capped at 0x1fff and 0x2000.
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:param channel: RTIO channel number of this interface.
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:param core_device: Core device name.
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"""
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kernel_invariants = {
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"core", "channel", "target_base", "target_read",
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"target_gain", "target_offset", "target_clr"
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@ -29,30 +46,87 @@ class Config:
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@kernel
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def set_clr(self, clr):
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"""Set/Unset waveform phase clear bits.
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Each bit corresponds to a Shuttler waveform generator core. Setting a
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clear bit forces the Shuttler core to clear the phase accumulator on
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waveform trigger (See :class:`Trigger` for the trigger method).
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Otherwise, the phase accumulator increments from its original value.
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:param clr: Waveform phase clear bits. The MSB corresponds to Channel
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15, LSB corresponds to Channel 0.
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"""
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rtio_output(self.target_base | self.target_clr, clr)
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@kernel
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def set_gain(self, channel, gain):
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"""Set the 16-bits pre-DAC gain register of a Shuttler Core channel.
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The `gain` parameter represents the decimal portion of the gain
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factor. The MSB represents 0.5 and the sign bit. Hence, the valid
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total gain value (1 +/- 0.gain) ranges from 0.5 to 1.5 - LSB.
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:param channel: Shuttler Core channel to be configured.
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:param gain: Shuttler Core channel gain.
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"""
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rtio_output(self.target_base | self.target_gain | channel, gain)
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@kernel
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def get_gain(self, channel):
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"""Return the pre-DAC gain value of a Shuttler Core channel.
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:param channel: The Shuttler Core channel.
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:return: Pre-DAC gain value. See :meth:`set_gain`.
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"""
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rtio_output(self.target_base | self.target_gain |
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self.target_read | channel, 0)
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return rtio_input_data(self.channel)
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@kernel
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def set_offset(self, channel, offset):
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"""Set the 16-bits pre-DAC offset register of a Shuttler Core channel.
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.. seealso::
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:meth:`shuttler_volt_to_mu`
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:param channel: Shuttler Core channel to be configured.
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:param offset: Shuttler Core channel offset.
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"""
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rtio_output(self.target_base | self.target_offset | channel, offset)
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@kernel
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def get_offset(self, channel):
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"""Return the pre-DAC offset value of a Shuttler Core channel.
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:param channel: The Shuttler Core channel.
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:return: Pre-DAC offset value. See :meth:`set_offset`.
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"""
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rtio_output(self.target_base | self.target_offset |
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self.target_read | channel, 0)
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return rtio_input_data(self.channel)
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class Volt:
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"""Shuttler Core cubic DC-bias spline.
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A Shuttler channel can generate a waveform `w(t)` that is the sum of a
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cubic spline `a(t)` and a sinusoid modulated in amplitude by a cubic
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spline `b(t)` and in phase/frequency by a quadratic spline `c(t)`, where
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.. math::
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w(t) = a(t) + b(t) * cos(c(t))
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And `t` corresponds to time in seconds.
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This class controls the cubic spline `a(t)`, in which
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.. math::
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a(t) = p_0 + p_1t + \\frac{p_2t^2}{2} + \\frac{p_3t^3}{6}
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And `a(t)` is in Volt.
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:param channel: RTIO channel number of this DC-bias spline interface.
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:param core_device: Core device name.
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"""
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kernel_invariants = {"core", "channel", "target_o"}
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def __init__(self, dmgr, channel, core_device="core"):
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@ -62,6 +136,34 @@ class Volt:
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@kernel
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def set_waveform(self, a0: TInt32, a1: TInt32, a2: TInt64, a3: TInt64):
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"""Set the DC-bias spline waveform.
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Given `a(t)` as defined in :class:`Volt`, the coefficients should be
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configured by the following formulae.
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.. math::
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T &= 8*10^{-9}
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a_0 &= p_0
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a_1 &= p_1T + \\frac{p_2T^2}{2} + \\frac{p_3T^3}{6}
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a_2 &= p_2T^2 + p_3T^3
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a_3 &= p_3T^3
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:math:`a_0`, :math:`a_1`, :math:`a_2` and :math:`a_3` are 14, 30, 46
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and 46 bits in width respectively. See :meth:`shuttler_volt_to_mu` for
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machine unit conversion.
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Note: The waveform is not updated to the Shuttler core until
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triggered. See :class:`Trigger` for the update triggering mechanism.
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:param a0: The :math:`a_0` coefficient in machine unit.
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:param a1: The :math:`a_1` coefficient in machine unit.
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:param a2: The :math:`a_2` coefficient in machine unit.
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:param a3: The :math:`a_3` coefficient in machine unit.
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"""
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pdq_words = [
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a0,
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a1,
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@ -80,6 +182,30 @@ class Volt:
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class Dds:
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"""Shuttler Core DDS spline.
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A Shuttler channel can generate a waveform `w(t)` that is the sum of a
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cubic spline `a(t)` and a sinusoid modulated in amplitude by a cubic
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spline `b(t)` and in phase/frequency by a quadratic spline `c(t)`, where
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.. math::
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w(t) = a(t) + b(t) * cos(c(t))
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And `t` corresponds to time in seconds.
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This class controls the cubic spline `b(t)` and quadratic spline `c(t)`,
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in which
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.. math::
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b(t) &= g * (q_0 + q_1t + \\frac{q_2t^2}{2} + \\frac{q_3t^3}{6})
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c(t) &= r_0 + r_1t + \\frac{r_2t^2}{2}
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And `b(t)` is in Volt, `c(t)` is in number of turns. Note that `b(t)`
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contributes to a constant gain of :math:`g=1.64676`.
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:param channel: RTIO channel number of this DC-bias spline interface.
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:param core_device: Core device name.
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"""
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kernel_invariants = {"core", "channel", "target_o"}
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def __init__(self, dmgr, channel, core_device="core"):
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@ -90,6 +216,44 @@ class Dds:
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@kernel
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def set_waveform(self, b0: TInt32, b1: TInt32, b2: TInt64, b3: TInt64,
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c0: TInt32, c1: TInt32, c2: TInt32):
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"""Set the DDS spline waveform.
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Given `b(t)` and `c(t)` as defined in :class:`Dds`, the coefficients
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should be configured by the following formulae.
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.. math::
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T &= 8*10^{-9}
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b_0 &= q_0
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b_1 &= q_1T + \\frac{q_2T^2}{2} + \\frac{q_3T^3}{6}
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b_2 &= q_2T^2 + q_3T^3
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b_3 &= q_3T^3
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c_0 &= r_0
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c_1 &= r_1T + \\frac{r_2T^2}{2}
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c_2 &= r_2T^2
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:math:`b_0`, :math:`b_1`, :math:`b_2` and :math:`b_3` are 14, 30, 46
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and 46 bits in width respectively. See :meth:`shuttler_volt_to_mu` for
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machine unit conversion. :math:`c_0`, :math:`c_1` and :math:`c_2` are
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16, 32 and 32 bits in width respectively.
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Note: The waveform is not updated to the Shuttler core until
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triggered. See :class:`Trigger` for the update triggering mechanism.
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:param b0: The :math:`b_0` coefficient in machine unit.
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:param b1: The :math:`b_1` coefficient in machine unit.
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:param b2: The :math:`b_2` coefficient in machine unit.
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:param b3: The :math:`b_3` coefficient in machine unit.
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:param c0: The :math:`c_0` coefficient in machine unit.
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:param c1: The :math:`c_1` coefficient in machine unit.
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:param c2: The :math:`c_2` coefficient in machine unit.
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"""
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pdq_words = [
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b0,
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b1,
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@ -113,6 +277,11 @@ class Dds:
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class Trigger:
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"""Shuttler Core spline coefficients update trigger.
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:param channel: RTIO channel number of the trigger interface.
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:param core_device: Core device name.
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"""
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kernel_invariants = {"core", "channel", "target_o"}
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def __init__(self, dmgr, channel, core_device="core"):
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@ -122,6 +291,16 @@ class Trigger:
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@kernel
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def trigger(self, trig_out):
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"""Triggers coefficient update of (a) Shuttler core channel(s).
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Each bit corresponds to a Shuttler waveform generator core. Setting
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`trig_out` bits commits the pending coefficient update (from
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`set_waveform` in :class:`Volt` and :class:`Dds`) to the Shuttler core
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synchronously.
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:param trig_out: Coefficient update trigger bits. The MSB corresponds
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to Channel 15, LSB corresponds to Channel 0.
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"""
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rtio_output(self.target_o, trig_out)
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@ -157,6 +336,19 @@ _AD4115_REG_SETUPCON0 = 0x20
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class Relay:
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"""Shuttler AFE relay switches.
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It controls the AFE relay switches and the LEDs. Switch on the relay to
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enable AFE output; And off to disable the output. The LEDs indicates the
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relay status.
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.. note::
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The relay does not disable ADC measurements. Voltage of any channels
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can still be read by the ADC even after switching off the relays.
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:param spi_device: SPI bus device name.
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:param core_device: Core device name.
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"""
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kernel_invariant = {"core", "bus"}
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def __init__(self, dmgr, spi_device, core_device="core"):
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@ -165,15 +357,34 @@ class Relay:
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@kernel
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def init(self):
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"""Initialize SPI device.
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Configures the SPI bus to 16-bits, write-only, simultaneous relay
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switches and LED control.
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"""
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self.bus.set_config_mu(
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RELAY_SPI_CONFIG, 16, SPIT_RELAY_WR, CS_RELAY | CS_LED)
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@kernel
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def enable(self, en: TInt32):
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"""Enable/Disable relay switches of corresponding channels.
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Each bit corresponds to the relay switch of a channel. Asserting a bit
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turns on the corresponding relay switch; Deasserting the same bit
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turns off the switch instead.
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:param en: Switch enable bits. The MSB corresponds to Channel 15, LSB
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corresponds to Channel 0.
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"""
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self.bus.write(en << 16)
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class ADC:
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"""Shuttler AFE ADC (AD4115) driver.
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:param spi_device: SPI bus device name.
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:param core_device: Core device name.
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"""
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kernel_invariant = {"core", "bus"}
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def __init__(self, dmgr, spi_device, core_device="core"):
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@ -182,13 +393,26 @@ class ADC:
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@kernel
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def read_id(self) -> TInt32:
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"""Read the product ID of the ADC.
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The expected return value is 0x38DX, the 4 LSbs are don't cares.
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:return: The read-back product ID.
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"""
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return self.read16(_AD4115_REG_ID)
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@kernel
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def reset(self):
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# Hold DIN high for 64 cycles
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# However, asserting CS right after the 64 cycles seems to interrupt
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# the start-up sequence.
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"""AD4115 reset procedure.
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This performs a write operation of 96 serial clock cycles with DIN
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held at high. It resets the entire device, including the register
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contents.
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.. note::
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The datasheet only requires 64 cycles, but reaserting `CS_n` right
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after the transfer appears to interrupt the start-up sequence.
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"""
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self.bus.set_config_mu(ADC_SPI_CONFIG, 32, SPIT_ADC_WR, CS_ADC)
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self.bus.write(0xffffffff)
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self.bus.write(0xffffffff)
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@ -198,6 +422,11 @@ class ADC:
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@kernel
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def read8(self, addr: TInt32) -> TInt32:
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"""Read from 8 bit register.
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:param addr: Register address.
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:return: Read-back register content.
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"""
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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16, SPIT_ADC_RD, CS_ADC)
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@ -206,6 +435,11 @@ class ADC:
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@kernel
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def read16(self, addr: TInt32) -> TInt32:
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"""Read from 16 bit register.
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:param addr: Register address.
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:return: Read-back register content.
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"""
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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24, SPIT_ADC_RD, CS_ADC)
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@ -214,6 +448,11 @@ class ADC:
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@kernel
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def read24(self, addr: TInt32) -> TInt32:
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"""Read from 24 bit register.
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:param addr: Register address.
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:return: Read-back register content.
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"""
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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32, SPIT_ADC_RD, CS_ADC)
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@ -222,44 +461,102 @@ class ADC:
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@kernel
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def write8(self, addr: TInt32, data: TInt32):
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"""Write to 8 bit register.
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:param addr: Register address.
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:param data: Data to be written.
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"""
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END, 16, SPIT_ADC_WR, CS_ADC)
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self.bus.write(addr << 24 | (data & 0xff) << 16)
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@kernel
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def write16(self, addr: TInt32, data: TInt32):
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"""Write to 16 bit register.
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:param addr: Register address.
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:param data: Data to be written.
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"""
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END, 24, SPIT_ADC_WR, CS_ADC)
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self.bus.write(addr << 24 | (data & 0xffff) << 8)
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@kernel
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def write24(self, addr: TInt32, data: TInt32):
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"""Write to 24 bit register.
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:param addr: Register address.
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:param data: Data to be written.
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"""
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END, 32, SPIT_ADC_WR, CS_ADC)
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self.bus.write(addr << 24 | (data & 0xffffff))
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@kernel
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def read_ch(self, channel: TInt32) -> TFloat:
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"""Sample a Shuttler channel on the AFE.
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It performs a single conversion using profile 0 and setup 0, on the
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selected channel. The sample is then recovered and converted to volt.
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:param channel: Shuttler channel to be sampled.
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:return: Voltage sample in volt.
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"""
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# Always configure Profile 0 for single conversion
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self.write16(_AD4115_REG_CH0, 0x8000 | ((channel * 2 + 1) << 4))
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self.write16(_AD4115_REG_SETUPCON0, 0x1300)
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self.write16(_AD4115_REG_ADCMODE, 0x8010)
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self.single_conversion()
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delay(100*us)
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adc_code = self.read24(_AD4115_REG_DATA)
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return ((adc_code / (1 << 23)) - 1) * 2.5 / 0.1
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@kernel
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def single_conversion(self):
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"""Place the ADC in single conversion mode.
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The ADC returns to standby mode after the conversion is complete.
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"""
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self.write16(_AD4115_REG_ADCMODE, 0x8010)
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@kernel
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def standby(self):
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"""Place the ADC in standby mode and disables power down the clock.
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The ADC can be returned to single conversion mode by calling
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:meth:`single_conversion`.
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"""
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# Selecting internal XO (0b00) also disables clock during standby
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self.write16(_AD4115_REG_ADCMODE, 0x8020)
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@kernel
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def power_down(self):
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"""Place the ADC in power-down mode.
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The ADC must be reset before returning to other modes.
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.. note::
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The AD4115 datasheet suggests placing the ADC in standby mode
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before power-down. This is to prevent accidental entry into the
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power-down mode.
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.. seealso::
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:meth:`standby`
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|
||||
:meth:`power_up`
|
||||
|
||||
"""
|
||||
self.write16(_AD4115_REG_ADCMODE, 0x8030)
|
||||
|
||||
@kernel
|
||||
def exit_power_down(self):
|
||||
def power_up(self):
|
||||
"""Exit the ADC power-down mode.
|
||||
|
||||
The ADC should be in power-down mode before calling this method.
|
||||
|
||||
.. seealso::
|
||||
:meth:`power_down`
|
||||
"""
|
||||
self.reset()
|
||||
# Although the datasheet claims 500 us reset wait time, only waiting
|
||||
# for ~500 us can result in DOUT pin stuck in high
|
||||
|
|
@ -267,6 +564,30 @@ class ADC:
|
|||
|
||||
@kernel
|
||||
def calibrate(self, volts, trigger, config, samples=[-5.0, 0.0, 5.0]):
|
||||
"""Calibrate the Shuttler waveform generator using the ADC on the AFE.
|
||||
|
||||
It finds the average slope rate and average offset by samples, and
|
||||
compensate by writing the pre-DAC gain and offset registers in the
|
||||
configuration registers.
|
||||
|
||||
.. note::
|
||||
If the pre-calibration slope rate < 1, the calibration procedure
|
||||
will introduce a pre-DAC gain compensation. However, this may
|
||||
saturate the pre-DAC voltage code. (See :class:`Config` notes).
|
||||
Shuttler cannot cover the entire +/- 10 V range in this case.
|
||||
|
||||
.. seealso::
|
||||
:meth:`Config.set_gain`
|
||||
|
||||
:meth:`Config.set_offset`
|
||||
|
||||
:param volts: A list of all 16 cubic DC-bias spline.
|
||||
(See :class:`Volt`)
|
||||
:param trigger: The Shuttler spline coefficient update trigger.
|
||||
:param config: The Shuttler core configuration registers.
|
||||
:param samples: A list of sample voltages for calibration. There must
|
||||
be at least 2 samples to perform slope rate calculation.
|
||||
"""
|
||||
assert len(volts) == 16
|
||||
assert len(samples) > 1
|
||||
|
||||
|
|
|
|||
|
|
@ -143,6 +143,12 @@ DAC/ADC drivers
|
|||
.. automodule:: artiq.coredevice.fastino
|
||||
:members:
|
||||
|
||||
:mod:`artiq.coredevice.shuttler` module
|
||||
++++++++++++++++++++++++++++++++++++++++
|
||||
|
||||
.. automodule:: artiq.coredevice.shuttler
|
||||
:members:
|
||||
|
||||
|
||||
Miscellaneous
|
||||
-------------
|
||||
|
|
|
|||
Loading…
Reference in New Issue