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drtio: fix Sayma after 83abdd28

This commit is contained in:
Sebastien Bourdeauducq 2018-02-19 16:54:43 +08:00
parent f5831af535
commit 7376ab0ff8
1 changed files with 8 additions and 6 deletions
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14
artiq/gateware/targets/sayma_amc.py
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@ -290,14 +290,15 @@ class Master(MiniSoC, AMPSoC):
self.config["SI5324_AS_SYNTHESIZER"] = None self.config["SI5324_AS_SYNTHESIZER"] = None
self.comb += platform.request("sfp_tx_disable", 0).eq(0) self.comb += platform.request("sfp_tx_disable", 0).eq(0)
self.submodules.transceiver = gth_ultrascale.GTH( self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("si5324_clkout"), clock_pads=platform.request("si5324_clkout"),
data_pads=[platform.request("sfp", 0)], data_pads=[platform.request("sfp", 0)],
sys_clk_freq=self.clk_freq, sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq) rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})( self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})(
DRTIOMaster(self.transceiver.channels[0])) DRTIOMaster(self.drtio_transceiver.channels[0]))
self.csr_devices.append("drtio0") self.csr_devices.append("drtio0")
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
self.drtio0.aux_controller.bus) self.drtio0.aux_controller.bus)
@ -307,7 +308,7 @@ class Master(MiniSoC, AMPSoC):
self.add_memory_group("drtio_aux", ["drtio0_aux"]) self.add_memory_group("drtio_aux", ["drtio0_aux"])
rtio_clk_period = 1e9/rtio_clk_freq rtio_clk_period = 1e9/rtio_clk_freq
for gth in self.transceiver.gths: for gth in self.drtio_transceiver.gths:
platform.add_period_constraint(gth.txoutclk, rtio_clk_period) platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints( platform.add_false_path_constraints(
@ -390,14 +391,15 @@ class Satellite(BaseSoC):
self.csr_devices.append("rtio_moninj") self.csr_devices.append("rtio_moninj")
self.comb += platform.request("sfp_tx_disable", 0).eq(0) self.comb += platform.request("sfp_tx_disable", 0).eq(0)
self.submodules.transceiver = gth_ultrascale.GTH( self.submodules.drtio_transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("si5324_clkout"), clock_pads=platform.request("si5324_clkout"),
data_pads=[platform.request("sfp", 0)], data_pads=[platform.request("sfp", 0)],
sys_clk_freq=self.clk_freq, sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq) rtio_clk_freq=rtio_clk_freq)
self.csr_devices.append("drtio_transceiver")
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})
self.submodules.drtio0 = rx0(DRTIOSatellite( self.submodules.drtio0 = rx0(DRTIOSatellite(
self.transceiver.channels[0], rtio_channels)) self.drtio_transceiver.channels[0], rtio_channels))
self.csr_devices.append("drtio0") self.csr_devices.append("drtio0")
self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, self.add_wb_slave(self.mem_map["drtio_aux"], 0x800,
self.drtio0.aux_controller.bus) self.drtio0.aux_controller.bus)
@ -422,7 +424,7 @@ class Satellite(BaseSoC):
self.config["HAS_SI5324"] = None self.config["HAS_SI5324"] = None
rtio_clk_period = 1e9/rtio_clk_freq rtio_clk_period = 1e9/rtio_clk_freq
gth = self.transceiver.gths[0] gth = self.drtio_transceiver.gths[0]
platform.add_period_constraint(gth.txoutclk, rtio_clk_period) platform.add_period_constraint(gth.txoutclk, rtio_clk_period)
platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period)
platform.add_false_path_constraints( platform.add_false_path_constraints(