From 7376ab0ff8e3ca90d6cf83b9827fcfb3e86ddac4 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 19 Feb 2018 16:54:43 +0800 Subject: [PATCH] drtio: fix Sayma after 83abdd28 --- artiq/gateware/targets/sayma_amc.py | 14 ++++++++------ 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index b83f08cfb..501a4ff88 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -290,14 +290,15 @@ class Master(MiniSoC, AMPSoC): self.config["SI5324_AS_SYNTHESIZER"] = None self.comb += platform.request("sfp_tx_disable", 0).eq(0) - self.submodules.transceiver = gth_ultrascale.GTH( + self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=platform.request("si5324_clkout"), data_pads=[platform.request("sfp", 0)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) + self.csr_devices.append("drtio_transceiver") self.submodules.drtio0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})( - DRTIOMaster(self.transceiver.channels[0])) + DRTIOMaster(self.drtio_transceiver.channels[0])) self.csr_devices.append("drtio0") self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, self.drtio0.aux_controller.bus) @@ -307,7 +308,7 @@ class Master(MiniSoC, AMPSoC): self.add_memory_group("drtio_aux", ["drtio0_aux"]) rtio_clk_period = 1e9/rtio_clk_freq - for gth in self.transceiver.gths: + for gth in self.drtio_transceiver.gths: platform.add_period_constraint(gth.txoutclk, rtio_clk_period) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints( @@ -390,14 +391,15 @@ class Satellite(BaseSoC): self.csr_devices.append("rtio_moninj") self.comb += platform.request("sfp_tx_disable", 0).eq(0) - self.submodules.transceiver = gth_ultrascale.GTH( + self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=platform.request("si5324_clkout"), data_pads=[platform.request("sfp", 0)], sys_clk_freq=self.clk_freq, rtio_clk_freq=rtio_clk_freq) + self.csr_devices.append("drtio_transceiver") rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.drtio0 = rx0(DRTIOSatellite( - self.transceiver.channels[0], rtio_channels)) + self.drtio_transceiver.channels[0], rtio_channels)) self.csr_devices.append("drtio0") self.add_wb_slave(self.mem_map["drtio_aux"], 0x800, self.drtio0.aux_controller.bus) @@ -422,7 +424,7 @@ class Satellite(BaseSoC): self.config["HAS_SI5324"] = None rtio_clk_period = 1e9/rtio_clk_freq - gth = self.transceiver.gths[0] + gth = self.drtio_transceiver.gths[0] platform.add_period_constraint(gth.txoutclk, rtio_clk_period) platform.add_period_constraint(gth.rxoutclk, rtio_clk_period) platform.add_false_path_constraints(