forked from M-Labs/artiq
jdcg: STPL tests now perform after DAC initialization
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parent
3f631c417d
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73271600a1
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@ -108,10 +108,6 @@ pub mod jdac {
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basic_request(dacno, jdac_common::PRBS, 0)?;
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jesd::prbs(dacno, false);
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jesd::stpl(dacno, true);
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basic_request(dacno, jdac_common::STPL, 0)?;
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jesd::stpl(dacno, false);
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basic_request(dacno, jdac_common::INIT, 0)?;
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clock::spin_us(5000);
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@ -120,7 +116,22 @@ pub mod jdac {
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return Err("JESD core reported bad SYNC");
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}
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info!(" ...done");
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info!(" ...done initializing");
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}
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Ok(())
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}
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pub fn stpl() -> Result<(), &'static str> {
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for dacno in 0..csr::JDCG.len() {
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let dacno = dacno as u8;
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info!("Running STPL test on DAC-{}...", dacno);
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jesd::stpl(dacno, true);
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basic_request(dacno, jdac_common::STPL, 0)?;
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jesd::stpl(dacno, false);
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info!(" ...done STPL test");
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}
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Ok(())
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}
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@ -609,6 +609,7 @@ pub extern fn main() -> i32 {
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jdcg::jesd::reset(false);
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let _ = jdcg::jdac::init();
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jdcg::jesd204sync::sysref_auto_align();
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jdcg::jdac::stpl();
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unsafe {
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csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); // unhide
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}
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