From 73271600a1fcccc40ff1365ddb8980dccf6b3053 Mon Sep 17 00:00:00 2001 From: Harry Ho Date: Thu, 10 Dec 2020 16:30:28 +0800 Subject: [PATCH] jdcg: STPL tests now perform after DAC initialization --- artiq/firmware/satman/jdcg.rs | 21 ++++++++++++++++----- artiq/firmware/satman/main.rs | 1 + 2 files changed, 17 insertions(+), 5 deletions(-) diff --git a/artiq/firmware/satman/jdcg.rs b/artiq/firmware/satman/jdcg.rs index c581791a3..c8a34827b 100644 --- a/artiq/firmware/satman/jdcg.rs +++ b/artiq/firmware/satman/jdcg.rs @@ -108,10 +108,6 @@ pub mod jdac { basic_request(dacno, jdac_common::PRBS, 0)?; jesd::prbs(dacno, false); - jesd::stpl(dacno, true); - basic_request(dacno, jdac_common::STPL, 0)?; - jesd::stpl(dacno, false); - basic_request(dacno, jdac_common::INIT, 0)?; clock::spin_us(5000); @@ -120,7 +116,22 @@ pub mod jdac { return Err("JESD core reported bad SYNC"); } - info!(" ...done"); + info!(" ...done initializing"); + } + Ok(()) + } + + pub fn stpl() -> Result<(), &'static str> { + for dacno in 0..csr::JDCG.len() { + let dacno = dacno as u8; + + info!("Running STPL test on DAC-{}...", dacno); + + jesd::stpl(dacno, true); + basic_request(dacno, jdac_common::STPL, 0)?; + jesd::stpl(dacno, false); + + info!(" ...done STPL test"); } Ok(()) } diff --git a/artiq/firmware/satman/main.rs b/artiq/firmware/satman/main.rs index 60f0f4c0a..e8dfb3584 100644 --- a/artiq/firmware/satman/main.rs +++ b/artiq/firmware/satman/main.rs @@ -609,6 +609,7 @@ pub extern fn main() -> i32 { jdcg::jesd::reset(false); let _ = jdcg::jdac::init(); jdcg::jesd204sync::sysref_auto_align(); + jdcg::jdac::stpl(); unsafe { csr::drtio_transceiver::txenable_write(0xffffffffu32 as _); // unhide }