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rtio: do not attempt latency compensation in gateware

This commit is contained in:
Sebastien Bourdeauducq 2015-04-16 13:09:29 +08:00
parent 6215d63491
commit 71167b8adf
3 changed files with 6 additions and 14 deletions

View File

@ -318,9 +318,6 @@ class RTIO(Module):
self.specials += AsyncResetSynchronizer(self.cd_rio, self.specials += AsyncResetSynchronizer(self.cd_rio,
self.kcsrs.reset.storage) self.kcsrs.reset.storage)
# Latency compensation
# TODO
# Managers # Managers
self.submodules.counter = _RTIOCounter(counter_width) self.submodules.counter = _RTIOCounter(counter_width)

View File

@ -4,17 +4,15 @@ from artiq.gateware.rtio import rtlink
class RT2WB(Module): class RT2WB(Module):
def __init__(self, wb, address_width, o_latency=0, i_latency=0): def __init__(self, wb, address_width):
self.rtlink = rtlink.Interface( self.rtlink = rtlink.Interface(
rtlink.OInterface( rtlink.OInterface(
flen(wb.dat_w), flen(wb.dat_w),
address_width + 1, address_width + 1,
latency=o_latency,
suppress_nop=False), suppress_nop=False),
rtlink.IInterface( rtlink.IInterface(
flen(wb.dat_r), flen(wb.dat_r),
timestamped=False, timestamped=False)
latency=i_latency)
) )
# # # # # #

View File

@ -3,7 +3,7 @@ from migen.fhdl.std import *
class OInterface: class OInterface:
def __init__(self, data_width, address_width=0, def __init__(self, data_width, address_width=0,
fine_ts_width=0, latency=1, suppress_nop=True): fine_ts_width=0, suppress_nop=True):
self.stb = Signal() self.stb = Signal()
self.busy = Signal() self.busy = Signal()
@ -14,7 +14,6 @@ class OInterface:
if fine_ts_width: if fine_ts_width:
self.fine_ts = Signal(fine_ts_width) self.fine_ts = Signal(fine_ts_width)
self.latency = latency
self.suppress_nop = suppress_nop self.suppress_nop = suppress_nop
@classmethod @classmethod
@ -22,12 +21,12 @@ class OInterface:
return cls(get_data_width(other), return cls(get_data_width(other),
get_address_width(other), get_address_width(other),
get_fine_ts_width(other), get_fine_ts_width(other),
other.latency, other.suppress_nop) other.suppress_nop)
class IInterface: class IInterface:
def __init__(self, data_width, def __init__(self, data_width,
timestamped=True, fine_ts_width=0, latency=2): timestamped=True, fine_ts_width=0):
self.stb = Signal() self.stb = Signal()
if data_width: if data_width:
@ -35,7 +34,6 @@ class IInterface:
if fine_ts_width: if fine_ts_width:
self.fine_ts = Signal(fine_ts_width) self.fine_ts = Signal(fine_ts_width)
self.latency = latency
self.timestamped = timestamped self.timestamped = timestamped
assert(not fine_ts_width or timestamped) assert(not fine_ts_width or timestamped)
@ -43,8 +41,7 @@ class IInterface:
def like(cls, other): def like(cls, other):
return cls(get_data_width(other), return cls(get_data_width(other),
other.timestamped, other.timestamped,
get_fine_ts_width(other), get_fine_ts_width(other))
other.latency)
class Interface: class Interface: