From 71105fd0d79dcdfcb7d6d67370b796e49dd76075 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Tue, 8 Mar 2016 15:38:08 +0800 Subject: [PATCH] rtio: collision_error -> collision --- RELEASE_NOTES.rst | 2 ++ artiq/coredevice/__init__.py | 4 ++-- artiq/coredevice/exceptions.py | 2 +- artiq/gateware/rtio/analyzer.py | 2 +- artiq/gateware/rtio/core.py | 22 +++++++++++----------- artiq/protocols/analyzer.py | 2 +- artiq/runtime/rtio.c | 8 ++++---- artiq/runtime/rtio.h | 2 +- artiq/test/coredevice/test_rtio.py | 8 ++++---- 9 files changed, 27 insertions(+), 25 deletions(-) diff --git a/RELEASE_NOTES.rst b/RELEASE_NOTES.rst index 7ea7ce122..4c905ea5a 100644 --- a/RELEASE_NOTES.rst +++ b/RELEASE_NOTES.rst @@ -10,3 +10,5 @@ Release notes * Core device flash storage has moved due to increased runtime size. This requires reflashing the runtime and the flash storage filesystem image or erase and rewrite its entries. +* RTIOCollisionError has been renamed to RTIOCollision + \ No newline at end of file diff --git a/artiq/coredevice/__init__.py b/artiq/coredevice/__init__.py index 88de8cf7c..da8c72b1d 100644 --- a/artiq/coredevice/__init__.py +++ b/artiq/coredevice/__init__.py @@ -1,12 +1,12 @@ from artiq.coredevice import exceptions, dds, spi from artiq.coredevice.exceptions import (RTIOUnderflow, RTIOSequenceError, - RTIOCollisionError, RTIOOverflow, + RTIOCollision, RTIOOverflow, DDSBatchError, CacheError) from artiq.coredevice.dds import (PHASE_MODE_CONTINUOUS, PHASE_MODE_ABSOLUTE, PHASE_MODE_TRACKING) __all__ = [] -__all__ += ["RTIOUnderflow", "RTIOSequenceError", "RTIOCollisionError", +__all__ += ["RTIOUnderflow", "RTIOSequenceError", "RTIOCollision", "RTIOOverflow", "DDSBatchError", "CacheError"] __all__ += ["PHASE_MODE_CONTINUOUS", "PHASE_MODE_ABSOLUTE", "PHASE_MODE_TRACKING"] diff --git a/artiq/coredevice/exceptions.py b/artiq/coredevice/exceptions.py index 36314ed1a..aa00ad784 100644 --- a/artiq/coredevice/exceptions.py +++ b/artiq/coredevice/exceptions.py @@ -86,7 +86,7 @@ class RTIOSequenceError(Exception): """ artiq_builtin = True -class RTIOCollisionError(Exception): +class RTIOCollision(Exception): """Raised when an event is submitted on a given channel with the same coarse timestamp as the previous one but with a different fine timestamp. diff --git a/artiq/gateware/rtio/analyzer.py b/artiq/gateware/rtio/analyzer.py index 22eac2e35..ca66ee7bb 100644 --- a/artiq/gateware/rtio/analyzer.py +++ b/artiq/gateware/rtio/analyzer.py @@ -82,7 +82,7 @@ class MessageEncoder(Module, AutoCSR): rtio_core.counter.value_sys << rtio_core.fine_ts_width), ] for ename in ("o_underflow_reset", "o_sequence_error_reset", - "o_collision_error_reset", "i_overflow_reset"): + "o_collision_reset", "i_overflow_reset"): self.comb += \ If(getattr(kcsrs, ename).re, exception_stb.eq(1), diff --git a/artiq/gateware/rtio/core.py b/artiq/gateware/rtio/core.py index e258b2a04..0f84769e6 100644 --- a/artiq/gateware/rtio/core.py +++ b/artiq/gateware/rtio/core.py @@ -103,7 +103,7 @@ class _OutputManager(Module): self.underflow = Signal() # valid 1 cycle after we, pulsed self.sequence_error = Signal() - self.collision_error = Signal() + self.collision = Signal() # # # @@ -126,7 +126,7 @@ class _OutputManager(Module): # Special cases replace = Signal() sequence_error = Signal() - collision_error = Signal() + collision = Signal() any_error = Signal() nop = Signal() self.sync.rsys += [ @@ -140,10 +140,10 @@ class _OutputManager(Module): < buf.timestamp[fine_ts_width:]) ] if fine_ts_width: - self.sync.rsys += collision_error.eq( + self.sync.rsys += collision.eq( (self.ev.timestamp[fine_ts_width:] == buf.timestamp[fine_ts_width:]) & (self.ev.timestamp[:fine_ts_width] != buf.timestamp[:fine_ts_width])) - self.comb += any_error.eq(sequence_error | collision_error) + self.comb += any_error.eq(sequence_error | collision) if interface.suppress_nop: # disable NOP at reset: do not suppress a first write with all 0s nop_en = Signal(reset=0) @@ -163,7 +163,7 @@ class _OutputManager(Module): ] self.comb += [ self.sequence_error.eq(self.we & sequence_error), - self.collision_error.eq(self.we & collision_error) + self.collision.eq(self.we & collision) ] # Buffer read and FIFO write @@ -335,7 +335,7 @@ class _KernelCSRs(AutoCSR): self.o_status = CSRStatus(4) self.o_underflow_reset = CSR() self.o_sequence_error_reset = CSR() - self.o_collision_error_reset = CSR() + self.o_collision_reset = CSR() if data_width: self.i_data = CSRStatus(data_width) @@ -422,22 +422,22 @@ class RTIO(Module): underflow = Signal() sequence_error = Signal() - collision_error = Signal() + collision = Signal() self.sync.rsys += [ If(selected & self.kcsrs.o_underflow_reset.re, underflow.eq(0)), If(selected & self.kcsrs.o_sequence_error_reset.re, sequence_error.eq(0)), - If(selected & self.kcsrs.o_collision_error_reset.re, - collision_error.eq(0)), + If(selected & self.kcsrs.o_collision_reset.re, + collision.eq(0)), If(o_manager.underflow, underflow.eq(1)), If(o_manager.sequence_error, sequence_error.eq(1)), - If(o_manager.collision_error, collision_error.eq(1)) + If(o_manager.collision, collision.eq(1)) ] o_statuses.append(Cat(~o_manager.writable, underflow, sequence_error, - collision_error)) + collision)) if channel.interface.i is not None: i_manager = _InputManager(channel.interface.i, self.counter, diff --git a/artiq/protocols/analyzer.py b/artiq/protocols/analyzer.py index 440c3b593..46ca712ee 100644 --- a/artiq/protocols/analyzer.py +++ b/artiq/protocols/analyzer.py @@ -15,6 +15,6 @@ class ExceptionType(Enum): o_underflow_reset = 0b010000 o_sequence_error_reset = 0b010001 - o_collision_error_reset = 0b010010 + o_collision_reset = 0b010010 i_overflow_reset = 0b100000 diff --git a/artiq/runtime/rtio.c b/artiq/runtime/rtio.c index 34aca2d78..90dd7fb5e 100644 --- a/artiq/runtime/rtio.c +++ b/artiq/runtime/rtio.c @@ -33,10 +33,10 @@ static void rtio_process_exceptional_status( "RTIO sequence error at {0} mu, channel {1}", timestamp, channel, 0); } - if(status & RTIO_O_STATUS_COLLISION_ERROR) { - rtio_o_collision_error_reset_write(1); - artiq_raise_from_c("RTIOCollisionError", - "RTIO collision error at {0} mu, channel {1}", + if(status & RTIO_O_STATUS_COLLISION) { + rtio_o_collision_reset_write(1); + artiq_raise_from_c("RTIOCollision", + "RTIO collision at {0} mu, channel {1}", timestamp, channel, 0); } } diff --git a/artiq/runtime/rtio.h b/artiq/runtime/rtio.h index a1ab8a90a..c32dca484 100644 --- a/artiq/runtime/rtio.h +++ b/artiq/runtime/rtio.h @@ -6,7 +6,7 @@ #define RTIO_O_STATUS_FULL 1 #define RTIO_O_STATUS_UNDERFLOW 2 #define RTIO_O_STATUS_SEQUENCE_ERROR 4 -#define RTIO_O_STATUS_COLLISION_ERROR 8 +#define RTIO_O_STATUS_COLLISION 8 #define RTIO_I_STATUS_EMPTY 1 #define RTIO_I_STATUS_OVERFLOW 2 diff --git a/artiq/test/coredevice/test_rtio.py b/artiq/test/coredevice/test_rtio.py index d110965f3..9caccc68b 100644 --- a/artiq/test/coredevice/test_rtio.py +++ b/artiq/test/coredevice/test_rtio.py @@ -150,7 +150,7 @@ class SequenceError(EnvExperiment): self.ttl_out.pulse(25*us) -class CollisionError(EnvExperiment): +class Collision(EnvExperiment): def build(self): self.setattr_device("core") self.setattr_device("ttl_out_serdes") @@ -220,9 +220,9 @@ class CoredeviceTest(ExperimentCase): with self.assertRaises(RTIOSequenceError): self.execute(SequenceError) - def test_collision_error(self): - with self.assertRaises(RTIOCollisionError): - self.execute(CollisionError) + def test_collision(self): + with self.assertRaises(RTIOCollision): + self.execute(Collision) def test_watchdog(self): # watchdog only works on the device