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drtio: drive SFP TX disable pins

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This commit is contained in:
Sebastien Bourdeauducq 2017-12-23 22:58:51 +08:00
parent 00ed51f6f4
commit 70b7f28ad3
2 changed files with 6 additions and 4 deletions
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5
artiq/gateware/targets/sayma_amc_drtio_master.py
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@ -53,10 +53,11 @@ class Master(MiniSoC, AMPSoC):
self.config["HAS_SI5324"] = None self.config["HAS_SI5324"] = None
self.config["SI5324_FREE_RUNNING"] = None self.config["SI5324_FREE_RUNNING"] = None
self.comb += platform.request("sfp_tx_disable_n", 0).eq(1)
self.submodules.transceiver = gth_ultrascale.GTH( self.submodules.transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("si5324_clkout"), clock_pads=platform.request("si5324_clkout"),
tx_pads=[platform.request("sfp_tx")], tx_pads=[platform.request("sfp_tx", 0)],
rx_pads=[platform.request("sfp_rx")], rx_pads=[platform.request("sfp_rx", 0)],
sys_clk_freq=self.clk_freq, sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq) rtio_clk_freq=rtio_clk_freq)

5
artiq/gateware/targets/sayma_amc_drtio_satellite.py
View File

@ -55,10 +55,11 @@ class Satellite(BaseSoC):
self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
self.csr_devices.append("rtio_moninj") self.csr_devices.append("rtio_moninj")
self.comb += platform.request("sfp_tx_disable_n", 0).eq(1)
self.submodules.transceiver = gth_ultrascale.GTH( self.submodules.transceiver = gth_ultrascale.GTH(
clock_pads=platform.request("si5324_clkout"), clock_pads=platform.request("si5324_clkout"),
tx_pads=[platform.request("sfp_tx")], tx_pads=[platform.request("sfp_tx", 0)],
rx_pads=[platform.request("sfp_rx")], rx_pads=[platform.request("sfp_rx", 0)],
sys_clk_freq=self.clk_freq, sys_clk_freq=self.clk_freq,
rtio_clk_freq=rtio_clk_freq) rtio_clk_freq=rtio_clk_freq)
rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"})