From 6d26def3ce6c89f33d6affec58e658c87a09d67d Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 6 Feb 2020 22:28:49 +0800 Subject: [PATCH] sayma: drive filtered_clk_sel on master variant --- artiq/gateware/targets/sayma_amc.py | 1 + 1 file changed, 1 insertion(+) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index e75c6d67a..18e6f70e0 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -388,6 +388,7 @@ class Master(MiniSoC, AMPSoC): self.config["SI5324_AS_SYNTHESIZER"] = None self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) + self.comb += platform.request("filtered_clk_sel").eq(1) self.comb += platform.request("sfp_tx_disable", 0).eq(0) self.submodules.drtio_transceiver = gth_ultrascale.GTH( clock_pads=platform.request("cdr_clk_clean", 0),