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si549: cleanups

This commit is contained in:
Sebastien Bourdeauducq 2019-11-28 16:36:59 +08:00
parent bcd2383c9d
commit 68cab5be8c
2 changed files with 14 additions and 5 deletions
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16
artiq/firmware/libboard_artiq/wrpll.rs
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@ -238,7 +238,9 @@ mod si549 {
clock::spin_us(50_000); // required? not specified in datasheet. clock::spin_us(50_000); // required? not specified in datasheet.
write(dcxo, 255, 0x00)?; // PAGE write(dcxo, 255, 0x00)?; // PAGE
write(dcxo, 69, 0x00)?; // Disable FCAL override. Should bit 0 be 1? write(dcxo, 69, 0x00)?; // Disable FCAL override.
// Note: Value 0x00 from Table 5.6 is inconsistent with Table 5.7,
// which shows bit 0 as reserved and =1.
write(dcxo, 17, 0x00)?; // Synchronously disable output write(dcxo, 17, 0x00)?; // Synchronously disable output
// The Si549 has no ID register, so we check that it responds correctly // The Si549 has no ID register, so we check that it responds correctly
@ -269,8 +271,16 @@ mod si549 {
pub fn init() { pub fn init() {
info!("initializing..."); info!("initializing...");
si549::program(i2c::Dcxo::Main, 0x017, 2, 0x04b5badb98a).expect("cannot initialize main Si549");
si549::program(i2c::Dcxo::Helper, 0x017, 2, 0x04b5c447213).expect("cannot initialize helper Si549"); #[cfg(rtio_frequency = "125.0")]
let (m_hsdiv, m_lsdiv, m_fbdiv) = (0x017, 2, 0x04b5badb98a);
#[cfg(rtio_frequency = "125.0")]
let (h_hsdiv, h_lsdiv, h_fbdiv) = (0x017, 2, 0x04b5c447213);
si549::program(i2c::Dcxo::Main, m_hsdiv, m_lsdiv, m_fbdiv)
.expect("cannot initialize main Si549");
si549::program(i2c::Dcxo::Helper, h_hsdiv, h_lsdiv, h_fbdiv)
.expect("cannot initialize helper Si549");
} }
pub fn select_recovered_clock(rc: bool) { pub fn select_recovered_clock(rc: bool) {

1
artiq/gateware/targets/sayma_amc.py
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@ -131,7 +131,6 @@ class SatelliteBase(MiniSoC):
self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
if with_wrpll: if with_wrpll:
# TODO: check OE polarity (depends on what was installed on the boards)
self.comb += [ self.comb += [
platform.request("filtered_clk_sel").eq(0), platform.request("filtered_clk_sel").eq(0),
platform.request("ddmtd_main_dcxo_oe").eq(1), platform.request("ddmtd_main_dcxo_oe").eq(1),