From 68cab5be8c6107b9121dafb51565a25b4f97a19a Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 28 Nov 2019 16:36:59 +0800 Subject: [PATCH] si549: cleanups --- artiq/firmware/libboard_artiq/wrpll.rs | 18 ++++++++++++++---- artiq/gateware/targets/sayma_amc.py | 1 - 2 files changed, 14 insertions(+), 5 deletions(-) diff --git a/artiq/firmware/libboard_artiq/wrpll.rs b/artiq/firmware/libboard_artiq/wrpll.rs index 01a3e89d5..125b47e69 100644 --- a/artiq/firmware/libboard_artiq/wrpll.rs +++ b/artiq/firmware/libboard_artiq/wrpll.rs @@ -234,11 +234,13 @@ mod si549 { i2c::init(dcxo)?; write(dcxo, 255, 0x00)?; // PAGE - write_no_ack_value(dcxo, 7, 0x80)?; // RESET + write_no_ack_value(dcxo, 7, 0x80)?; // RESET clock::spin_us(50_000); // required? not specified in datasheet. write(dcxo, 255, 0x00)?; // PAGE - write(dcxo, 69, 0x00)?; // Disable FCAL override. Should bit 0 be 1? + write(dcxo, 69, 0x00)?; // Disable FCAL override. + // Note: Value 0x00 from Table 5.6 is inconsistent with Table 5.7, + // which shows bit 0 as reserved and =1. write(dcxo, 17, 0x00)?; // Synchronously disable output // The Si549 has no ID register, so we check that it responds correctly @@ -269,8 +271,16 @@ mod si549 { pub fn init() { info!("initializing..."); - si549::program(i2c::Dcxo::Main, 0x017, 2, 0x04b5badb98a).expect("cannot initialize main Si549"); - si549::program(i2c::Dcxo::Helper, 0x017, 2, 0x04b5c447213).expect("cannot initialize helper Si549"); + + #[cfg(rtio_frequency = "125.0")] + let (m_hsdiv, m_lsdiv, m_fbdiv) = (0x017, 2, 0x04b5badb98a); + #[cfg(rtio_frequency = "125.0")] + let (h_hsdiv, h_lsdiv, h_fbdiv) = (0x017, 2, 0x04b5c447213); + + si549::program(i2c::Dcxo::Main, m_hsdiv, m_lsdiv, m_fbdiv) + .expect("cannot initialize main Si549"); + si549::program(i2c::Dcxo::Helper, h_hsdiv, h_lsdiv, h_fbdiv) + .expect("cannot initialize helper Si549"); } pub fn select_recovered_clock(rc: bool) { diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index dc5d37a6a..4e2341037 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -131,7 +131,6 @@ class SatelliteBase(MiniSoC): self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) if with_wrpll: - # TODO: check OE polarity (depends on what was installed on the boards) self.comb += [ platform.request("filtered_clk_sel").eq(0), platform.request("ddmtd_main_dcxo_oe").eq(1),