forked from M-Labs/artiq
sawg: adapt to int32/int64 change
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@ -1,3 +1,4 @@
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from numpy import int32, int64
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from artiq.language.core import kernel, now_mu, portable
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from artiq.language.core import kernel, now_mu, portable
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from artiq.coredevice.rtio import rtio_output, rtio_output_list
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from artiq.coredevice.rtio import rtio_output, rtio_output_list
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from artiq.language.types import TInt32, TInt64, TFloat, TList
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from artiq.language.types import TInt32, TInt64, TFloat, TList
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@ -25,8 +26,8 @@ class Spline:
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@portable(flags=["fast-math"])
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@portable(flags=["fast-math"])
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def to_mu64(self, value: TFloat) -> TList(TInt32):
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def to_mu64(self, value: TFloat) -> TList(TInt32):
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v = int(round(value*self.scale), width=64)
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v = int64(round(value*self.scale))
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return [int(v, width=32), int(v >> 32, width=32)]
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return [int32(v), int32(v >> 32)]
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@kernel
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@kernel
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def set_mu(self, value: TInt32):
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def set_mu(self, value: TInt32):
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@ -68,7 +69,7 @@ class Spline:
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j = 0
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j = 0
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for i, vi in enumerate(value):
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for i, vi in enumerate(value):
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w = self.width + i*self.time_width
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w = self.width + i*self.time_width
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vi = int(round(vi*(self.scale*self.time_scale**i)), width=64)
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vi = int64(round(vi*(self.scale*self.time_scale**i)))
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for k in range(0, w, 16):
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for k in range(0, w, 16):
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wi = (vi >> k) & 0xffff
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wi = (vi >> k) & 0xffff
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v[j//2] += wi << (16 * ((j + 1)//2 - j//2))
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v[j//2] += wi << (16 * ((j + 1)//2 - j//2))
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@ -1,5 +1,6 @@
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import unittest
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import unittest
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import numpy as np
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import numpy as np
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from numpy import int32, int64
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import migen as mg
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import migen as mg
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@ -19,18 +20,10 @@ class RTIOManager:
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def rtio_output_list(self, *args, **kwargs):
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def rtio_output_list(self, *args, **kwargs):
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self.rtio_output(*args, **kwargs)
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self.rtio_output(*args, **kwargs)
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def int(self, value, width=32):
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if width == 32:
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return np.int32(value)
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elif width == 64:
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return np.int64(value)
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else:
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raise ValueError(width)
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def patch(self, mod):
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def patch(self, mod):
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assert not getattr(mod, "_saved", None)
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assert not getattr(mod, "_saved", None)
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mod._saved = {}
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mod._saved = {}
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for name in "rtio_output rtio_output_list int".split():
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for name in "rtio_output rtio_output_list".split():
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mod._saved[name] = getattr(mod, name, None)
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mod._saved[name] = getattr(mod, name, None)
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setattr(mod, name, getattr(self, name))
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setattr(mod, name, getattr(self, name))
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@ -47,7 +40,7 @@ class SAWGTest(unittest.TestCase):
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self.core = sim_devices.Core({})
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self.core = sim_devices.Core({})
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self.core.coarse_ref_period = 8
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self.core.coarse_ref_period = 8
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self.channel = mg.ClockDomainsRenamer({"rio_phy": "sys"})(
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self.channel = mg.ClockDomainsRenamer({"rio_phy": "sys"})(
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Channel(width=16, parallelism=4))
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Channel(width=16, parallelism=2))
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self.driver = sawg.SAWG({"core": self.core}, channel_base=0,
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self.driver = sawg.SAWG({"core": self.core}, channel_base=0,
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parallelism=self.channel.parallelism)
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parallelism=self.channel.parallelism)
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@ -68,9 +61,9 @@ class SAWGTest(unittest.TestCase):
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self.rtio_manager.outputs, [
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self.rtio_manager.outputs, [
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(0, 1, 0, int(round(
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(0, 1, 0, int(round(
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(1 << self.driver.offset.width - 1)*.9))),
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(1 << self.driver.offset.width - 1)*.9))),
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(2*8, 8, 0, [0, int(round(
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(2*8, 8, 0, [int(round(
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(1 << self.driver.frequency0.width - 1) *
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(1 << self.driver.frequency0.width) /
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self.channel.parallelism*.1))]),
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self.channel.parallelism*.1)), 0]),
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(4*8, 1, 0, 0),
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(4*8, 1, 0, 0),
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])
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])
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