diff --git a/artiq/coredevice/sawg.py b/artiq/coredevice/sawg.py
index d90eba9ed..6823bcf6d 100644
--- a/artiq/coredevice/sawg.py
+++ b/artiq/coredevice/sawg.py
@@ -1,3 +1,4 @@
+from numpy import int32, int64
 from artiq.language.core import kernel, now_mu, portable
 from artiq.coredevice.rtio import rtio_output, rtio_output_list
 from artiq.language.types import TInt32, TInt64, TFloat, TList
@@ -25,8 +26,8 @@ class Spline:
 
     @portable(flags=["fast-math"])
     def to_mu64(self, value: TFloat) -> TList(TInt32):
-        v = int(round(value*self.scale), width=64)
-        return [int(v, width=32), int(v >> 32, width=32)]
+        v = int64(round(value*self.scale))
+        return [int32(v), int32(v >> 32)]
 
     @kernel
     def set_mu(self, value: TInt32):
@@ -68,7 +69,7 @@ class Spline:
         j = 0
         for i, vi in enumerate(value):
             w = self.width + i*self.time_width
-            vi = int(round(vi*(self.scale*self.time_scale**i)), width=64)
+            vi = int64(round(vi*(self.scale*self.time_scale**i)))
             for k in range(0, w, 16):
                 wi = (vi >> k) & 0xffff
                 v[j//2] += wi << (16 * ((j + 1)//2 - j//2))
diff --git a/artiq/test/gateware/test_sawg_fe.py b/artiq/test/gateware/test_sawg_fe.py
index 325709340..bb1d03478 100644
--- a/artiq/test/gateware/test_sawg_fe.py
+++ b/artiq/test/gateware/test_sawg_fe.py
@@ -1,5 +1,6 @@
 import unittest
 import numpy as np
+from numpy import int32, int64
 
 import migen as mg
 
@@ -19,18 +20,10 @@ class RTIOManager:
     def rtio_output_list(self, *args, **kwargs):
         self.rtio_output(*args, **kwargs)
 
-    def int(self, value, width=32):
-        if width == 32:
-            return np.int32(value)
-        elif width == 64:
-            return np.int64(value)
-        else:
-            raise ValueError(width)
-
     def patch(self, mod):
         assert not getattr(mod, "_saved", None)
         mod._saved = {}
-        for name in "rtio_output rtio_output_list int".split():
+        for name in "rtio_output rtio_output_list".split():
             mod._saved[name] = getattr(mod, name, None)
             setattr(mod, name, getattr(self, name))
 
@@ -47,7 +40,7 @@ class SAWGTest(unittest.TestCase):
         self.core = sim_devices.Core({})
         self.core.coarse_ref_period = 8
         self.channel = mg.ClockDomainsRenamer({"rio_phy": "sys"})(
-            Channel(width=16, parallelism=4))
+            Channel(width=16, parallelism=2))
         self.driver = sawg.SAWG({"core": self.core}, channel_base=0,
                                 parallelism=self.channel.parallelism)
 
@@ -68,9 +61,9 @@ class SAWGTest(unittest.TestCase):
             self.rtio_manager.outputs, [
                 (0, 1, 0, int(round(
                     (1 << self.driver.offset.width - 1)*.9))),
-                (2*8, 8, 0, [0, int(round(
-                    (1 << self.driver.frequency0.width - 1) *
-                    self.channel.parallelism*.1))]),
+                (2*8, 8, 0, [int(round(
+                    (1 << self.driver.frequency0.width) /
+                    self.channel.parallelism*.1)), 0]),
                 (4*8, 1, 0, 0),
             ])