From 66b3132c28c4e8a02ee1c7169606b06dbc4f3c7b Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Sun, 6 Jan 2019 14:54:32 +0800 Subject: [PATCH] sayma_amc: fix RTIO TSC instantiation --- artiq/gateware/targets/sayma_amc.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 3561eb7b6..efefc2f45 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -287,7 +287,7 @@ class MasterDAC(MiniSoC, AMPSoC, RTMCommon): rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") - self.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) + self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) drtio_csr_group = [] drtioaux_csr_group = [] @@ -452,7 +452,7 @@ class Master(MiniSoC, AMPSoC): rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") - self.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) + self.submodules.rtio_tsc = rtio.TSC("async", glbl_fine_ts_width=3) drtio_csr_group = [] drtioaux_csr_group = [] @@ -623,7 +623,7 @@ class Satellite(BaseSoC, RTMCommon): rtio_clk_freq=rtio_clk_freq) self.csr_devices.append("drtio_transceiver") - self.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) + self.submodules.rtio_tsc = rtio.TSC("sync", glbl_fine_ts_width=3) rx0 = ClockDomainsRenamer({"rtio_rx": "rtio_rx0"}) self.submodules.rx_synchronizer = rx0(XilinxRXSynchronizer())