From 65567e1201f7341a23aeb38900e15ce7cc3a8c9a Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 21 Nov 2014 15:51:51 -0800
Subject: [PATCH] soc/target: remap RTIO to avoid conflict with Ethernet
 MAC+PHY

---
 soc/targets/artiq.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/soc/targets/artiq.py b/soc/targets/artiq.py
index aff07b227..a57a38111 100644
--- a/soc/targets/artiq.py
+++ b/soc/targets/artiq.py
@@ -41,7 +41,7 @@ class _TestGen(Module):
 
 class ARTIQMiniSoC(BaseSoC):
     csr_map = {
-        "rtio":            12
+        "rtio":            13
     }
     csr_map.update(BaseSoC.csr_map)