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targets/kc705_drtio: remove DAC FMC card support

This commit is contained in:
Sebastien Bourdeauducq 2017-12-15 17:32:25 +08:00
parent f02c74cb7b
commit 649b60ea29
2 changed files with 0 additions and 14 deletions

View File

@ -9,7 +9,6 @@ from misoc.cores import spi as spi_csr
from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
from misoc.integration.builder import builder_args, builder_argdict from misoc.integration.builder import builder_args, builder_argdict
from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
from artiq.gateware.amp import AMPSoC, build_artiq_soc from artiq.gateware.amp import AMPSoC, build_artiq_soc
from artiq.gateware import rtio from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple from artiq.gateware.rtio.phy import ttl_simple
@ -63,12 +62,6 @@ class Master(MiniSoC, AMPSoC):
self.add_csr_group("drtio", ["drtio0"]) self.add_csr_group("drtio", ["drtio0"])
self.add_memory_group("drtio_aux", ["drtio0_aux"]) self.add_memory_group("drtio_aux", ["drtio0_aux"])
platform.add_extension(ad9154_fmc_ebz)
ad9154_spi = platform.request("ad9154_spi")
self.comb += ad9154_spi.en.eq(1)
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
self.csr_devices.append("converter_spi")
self.comb += [ self.comb += [
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")), platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
platform.request("user_sma_clock_n").eq(ClockSignal("rtio")) platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))

View File

@ -10,7 +10,6 @@ from misoc.cores import gpio
from misoc.integration.builder import * from misoc.integration.builder import *
from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict
from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
from artiq.gateware import rtio from artiq.gateware import rtio
from artiq.gateware.rtio.phy import ttl_simple from artiq.gateware.rtio.phy import ttl_simple
from artiq.gateware.drtio.transceiver import gtx_7series from artiq.gateware.drtio.transceiver import gtx_7series
@ -85,12 +84,6 @@ class Satellite(BaseSoC):
self.config["I2C_BUS_COUNT"] = 1 self.config["I2C_BUS_COUNT"] = 1
self.config["HAS_SI5324"] = None self.config["HAS_SI5324"] = None
platform.add_extension(ad9154_fmc_ebz)
ad9154_spi = platform.request("ad9154_spi")
self.comb += ad9154_spi.en.eq(1)
self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
self.csr_devices.append("converter_spi")
self.comb += [ self.comb += [
platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")), platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
platform.request("user_sma_clock_n").eq(ClockSignal("rtio")) platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))