From 649b60ea29c61e3871d4c002e7a573c9dcfa823f Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 15 Dec 2017 17:32:25 +0800 Subject: [PATCH] targets/kc705_drtio: remove DAC FMC card support --- artiq/gateware/targets/kc705_drtio_master.py | 7 ------- artiq/gateware/targets/kc705_drtio_satellite.py | 7 ------- 2 files changed, 14 deletions(-) diff --git a/artiq/gateware/targets/kc705_drtio_master.py b/artiq/gateware/targets/kc705_drtio_master.py index 0257b2e40..c1bf28fb4 100755 --- a/artiq/gateware/targets/kc705_drtio_master.py +++ b/artiq/gateware/targets/kc705_drtio_master.py @@ -9,7 +9,6 @@ from misoc.cores import spi as spi_csr from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict from misoc.integration.builder import builder_args, builder_argdict -from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz from artiq.gateware.amp import AMPSoC, build_artiq_soc from artiq.gateware import rtio from artiq.gateware.rtio.phy import ttl_simple @@ -63,12 +62,6 @@ class Master(MiniSoC, AMPSoC): self.add_csr_group("drtio", ["drtio0"]) self.add_memory_group("drtio_aux", ["drtio0_aux"]) - platform.add_extension(ad9154_fmc_ebz) - ad9154_spi = platform.request("ad9154_spi") - self.comb += ad9154_spi.en.eq(1) - self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi) - self.csr_devices.append("converter_spi") - self.comb += [ platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")), platform.request("user_sma_clock_n").eq(ClockSignal("rtio")) diff --git a/artiq/gateware/targets/kc705_drtio_satellite.py b/artiq/gateware/targets/kc705_drtio_satellite.py index cd882b3d5..0f318a0d3 100755 --- a/artiq/gateware/targets/kc705_drtio_satellite.py +++ b/artiq/gateware/targets/kc705_drtio_satellite.py @@ -10,7 +10,6 @@ from misoc.cores import gpio from misoc.integration.builder import * from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict -from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz from artiq.gateware import rtio from artiq.gateware.rtio.phy import ttl_simple from artiq.gateware.drtio.transceiver import gtx_7series @@ -85,12 +84,6 @@ class Satellite(BaseSoC): self.config["I2C_BUS_COUNT"] = 1 self.config["HAS_SI5324"] = None - platform.add_extension(ad9154_fmc_ebz) - ad9154_spi = platform.request("ad9154_spi") - self.comb += ad9154_spi.en.eq(1) - self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi) - self.csr_devices.append("converter_spi") - self.comb += [ platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")), platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))