forked from M-Labs/artiq
targets/kc705_drtio: remove DAC FMC card support
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@ -9,7 +9,6 @@ from misoc.cores import spi as spi_csr
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from misoc.targets.kc705 import MiniSoC, soc_kc705_args, soc_kc705_argdict
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from misoc.integration.builder import builder_args, builder_argdict
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from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
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from artiq.gateware.amp import AMPSoC, build_artiq_soc
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple
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@ -63,12 +62,6 @@ class Master(MiniSoC, AMPSoC):
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self.add_csr_group("drtio", ["drtio0"])
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self.add_memory_group("drtio_aux", ["drtio0_aux"])
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platform.add_extension(ad9154_fmc_ebz)
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ad9154_spi = platform.request("ad9154_spi")
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self.comb += ad9154_spi.en.eq(1)
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self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
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self.csr_devices.append("converter_spi")
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self.comb += [
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platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
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platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
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@ -10,7 +10,6 @@ from misoc.cores import gpio
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from misoc.integration.builder import *
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from misoc.targets.kc705 import BaseSoC, soc_kc705_args, soc_kc705_argdict
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from artiq.gateware.ad9154_fmc_ebz import ad9154_fmc_ebz
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from artiq.gateware import rtio
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from artiq.gateware.rtio.phy import ttl_simple
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from artiq.gateware.drtio.transceiver import gtx_7series
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@ -85,12 +84,6 @@ class Satellite(BaseSoC):
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self.config["I2C_BUS_COUNT"] = 1
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self.config["HAS_SI5324"] = None
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platform.add_extension(ad9154_fmc_ebz)
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ad9154_spi = platform.request("ad9154_spi")
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self.comb += ad9154_spi.en.eq(1)
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self.submodules.converter_spi = spi_csr.SPIMaster(ad9154_spi)
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self.csr_devices.append("converter_spi")
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self.comb += [
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platform.request("user_sma_clock_p").eq(ClockSignal("rtio_rx0")),
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platform.request("user_sma_clock_n").eq(ClockSignal("rtio"))
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