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Revert "fir: force dsp48" 

This reverts commit 0ad433832d1b6dcd803ffa086ae73b2ee0568326.
This commit is contained in:
Robert Jördens 2016-12-13 23:53:36 +01:00
parent 641d109786
commit 61abd994e9
2 changed files with 0 additions and 5 deletions
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2
artiq/gateware/dsp/fir.py
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@ -65,7 +65,6 @@ class FIR(Module):
if c == 0 or c in coefficients[i + 1:]: if c == 0 or c in coefficients[i + 1:]:
continue continue
m = Signal((width + shift, True)) m = Signal((width + shift, True))
m.attr.add("use_multiplier")
self.sync += m.eq(c*reduce(add, [ self.sync += m.eq(c*reduce(add, [
xj for xj, cj in zip(x[::-1], coefficients) if cj == c xj for xj, cj in zip(x[::-1], coefficients) if cj == c
])) ]))
@ -109,7 +108,6 @@ class ParallelFIR(Module):
if c == 0 or c in coefficients[i + 1:]: if c == 0 or c in coefficients[i + 1:]:
continue continue
m = Signal((width + shift, True)) m = Signal((width + shift, True))
m.attr.add("use_multiplier")
self.sync += m.eq(c*reduce(add, [ self.sync += m.eq(c*reduce(add, [
xj for xj, cj in zip(x[-1 - j::-1], coefficients) if cj == c xj for xj, cj in zip(x[-1 - j::-1], coefficients) if cj == c
])) ]))

3
artiq/gateware/targets/phaser.py
View File

@ -169,9 +169,6 @@ class Phaser(MiniSoC, AMPSoC):
ident=artiq_version, ident=artiq_version,
**kwargs) **kwargs)
AMPSoC.__init__(self) AMPSoC.__init__(self)
self.platform.toolchain.attr_translate["use_multiplier"] = \
("use_dsp48", "yes")
self.platform.toolchain.bitstream_commands.extend([ self.platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]", "set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
]) ])