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fir: force dsp48

This commit is contained in:
Robert Jördens 2016-12-13 22:32:27 +01:00
parent 8381db279f
commit 641d109786
2 changed files with 5 additions and 0 deletions
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2
artiq/gateware/dsp/fir.py
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@ -65,6 +65,7 @@ class FIR(Module):
if c == 0 or c in coefficients[i + 1:]:
continue
m = Signal((width + shift, True))
m.attr.add("use_multiplier")
self.sync += m.eq(c*reduce(add, [
xj for xj, cj in zip(x[::-1], coefficients) if cj == c
]))
@ -108,6 +109,7 @@ class ParallelFIR(Module):
if c == 0 or c in coefficients[i + 1:]:
continue
m = Signal((width + shift, True))
m.attr.add("use_multiplier")
self.sync += m.eq(c*reduce(add, [
xj for xj, cj in zip(x[-1 - j::-1], coefficients) if cj == c
]))

3
artiq/gateware/targets/phaser.py
View File

@ -169,6 +169,9 @@ class Phaser(MiniSoC, AMPSoC):
ident=artiq_version,
**kwargs)
AMPSoC.__init__(self)
self.platform.toolchain.attr_translate["use_multiplier"] = \
("use_dsp48", "yes")
self.platform.toolchain.bitstream_commands.extend([
"set_property BITSTREAM.GENERAL.COMPRESS True [current_design]",
])