From 60ad36e7d60216084e5f15d1c0288b7afd5ce46b Mon Sep 17 00:00:00 2001
From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Tue, 29 Aug 2017 13:43:26 +0200
Subject: [PATCH] gateware/serwb: generate wishbone error on wishbone slave
 when access while link is not ready

---
 artiq/gateware/serwb/etherbone.py              | 16 ++++++++++++----
 artiq/gateware/targets/sayma_amc_standalone.py |  1 +
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/artiq/gateware/serwb/etherbone.py b/artiq/gateware/serwb/etherbone.py
index 8add43044..a5dff54c0 100644
--- a/artiq/gateware/serwb/etherbone.py
+++ b/artiq/gateware/serwb/etherbone.py
@@ -645,6 +645,7 @@ class EtherboneWishboneMaster(Module):
 class EtherboneWishboneSlave(Module):
     def __init__(self):
         self.bus = bus = wishbone.Interface()
+        self.ready = Signal(reset=1)
         self.sink = sink = stream.Endpoint(etherbone_mmap_description(32))
         self.source = source = stream.Endpoint(etherbone_mmap_description(32))
 
@@ -654,10 +655,14 @@ class EtherboneWishboneSlave(Module):
         fsm.act("IDLE",
             sink.ack.eq(1),
             If(bus.stb & bus.cyc,
-                If(bus.we,
-                    NextState("SEND_WRITE")
+                If(self.ready,
+                    If(bus.we,
+                        NextState("SEND_WRITE")
+                    ).Else(
+                        NextState("SEND_READ")
+                    )
                 ).Else(
-                    NextState("SEND_READ")
+                    NextState("SEND_ERROR")
                 )
             )
         )
@@ -694,7 +699,10 @@ class EtherboneWishboneSlave(Module):
                 NextState("IDLE")
             )
         )
-
+        fsm.act("SEND_ERROR",
+            bus.ack.eq(1),
+            bus.err.eq(1)
+        )
 
 # etherbone
 
diff --git a/artiq/gateware/targets/sayma_amc_standalone.py b/artiq/gateware/targets/sayma_amc_standalone.py
index 836db203e..554964b74 100755
--- a/artiq/gateware/targets/sayma_amc_standalone.py
+++ b/artiq/gateware/targets/sayma_amc_standalone.py
@@ -86,6 +86,7 @@ class SaymaAMCStandalone(MiniSoC, AMPSoC):
         self.submodules += serwb_depacketizer, serwb_packetizer
         serwb_etherbone = serwb.etherbone.Etherbone(mode="slave")
         self.submodules += serwb_etherbone
+        self.comb += serwb_etherbone.wishbone.ready.eq(serwb_init.ready)
         serwb_tx_cdc = ClockDomainsRenamer({"write": "sys", "read": "serdes"})(
             stream.AsyncFIFO([("data", 32)], 8))
         self.submodules += serwb_tx_cdc