forked from M-Labs/artiq
kasli: ignore OSERDESE2->ISERDESE2 timing path on DRTIO targets as well
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416232cb64
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605292535c
@ -80,6 +80,17 @@ class _RTIOCRG(Module, AutoCSR):
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]
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def fix_serdes_timing_path(platform):
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# ignore timing of path from OSERDESE2 through the pad to ISERDESE2
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platform.add_platform_command(
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"set_false_path -quiet "
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"-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
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"-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
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"-to [get_pins -filter {{REF_PIN_NAME == D}} "
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"-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
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)
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class _StandaloneBase(MiniSoC, AMPSoC):
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mem_map = {
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"cri_con": 0x10000000,
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@ -114,6 +125,7 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk)
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self.csr_devices.append("rtio_crg")
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fix_serdes_timing_path(self.platform)
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self.submodules.rtio_core = rtio.Core(rtio_channels)
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self.csr_devices.append("rtio_core")
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self.submodules.rtio = rtio.KernelInitiator()
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@ -136,15 +148,6 @@ class _StandaloneBase(MiniSoC, AMPSoC):
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self.get_native_sdram_if())
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self.csr_devices.append("rtio_analyzer")
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# ignore timing of path from OSERDESE2 through the pad to ISERDESE2
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self.platform.add_platform_command(
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"set_false_path -quiet "
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"-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} "
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"-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] "
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"-to [get_pins -filter {{REF_PIN_NAME == D}} "
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"-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]"
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)
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def _eem_signal(i):
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n = "d{}".format(i)
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@ -686,6 +689,7 @@ class _MasterBase(MiniSoC, AMPSoC):
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self.crg.cd_sys.clk, gtp.rxoutclk)
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self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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@ -806,6 +810,7 @@ class _SatelliteBase(BaseSoC):
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gtp.txoutclk, gtp.rxoutclk)
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self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq)
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fix_serdes_timing_path(platform)
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def add_rtio(self, rtio_channels):
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self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)
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