From 605292535c5cc108b1d0a5de375da6a1c7797366 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Thu, 29 Mar 2018 10:12:02 +0800 Subject: [PATCH] kasli: ignore OSERDESE2->ISERDESE2 timing path on DRTIO targets as well --- artiq/gateware/targets/kasli.py | 23 ++++++++++++++--------- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/artiq/gateware/targets/kasli.py b/artiq/gateware/targets/kasli.py index 5923db950..22b6a3fbf 100755 --- a/artiq/gateware/targets/kasli.py +++ b/artiq/gateware/targets/kasli.py @@ -80,6 +80,17 @@ class _RTIOCRG(Module, AutoCSR): ] +def fix_serdes_timing_path(platform): + # ignore timing of path from OSERDESE2 through the pad to ISERDESE2 + platform.add_platform_command( + "set_false_path -quiet " + "-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} " + "-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] " + "-to [get_pins -filter {{REF_PIN_NAME == D}} " + "-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]" + ) + + class _StandaloneBase(MiniSoC, AMPSoC): mem_map = { "cri_con": 0x10000000, @@ -114,6 +125,7 @@ class _StandaloneBase(MiniSoC, AMPSoC): def add_rtio(self, rtio_channels): self.submodules.rtio_crg = _RTIOCRG(self.platform, self.crg.cd_sys.clk) self.csr_devices.append("rtio_crg") + fix_serdes_timing_path(self.platform) self.submodules.rtio_core = rtio.Core(rtio_channels) self.csr_devices.append("rtio_core") self.submodules.rtio = rtio.KernelInitiator() @@ -136,15 +148,6 @@ class _StandaloneBase(MiniSoC, AMPSoC): self.get_native_sdram_if()) self.csr_devices.append("rtio_analyzer") - # ignore timing of path from OSERDESE2 through the pad to ISERDESE2 - self.platform.add_platform_command( - "set_false_path -quiet " - "-through [get_pins -filter {{REF_PIN_NAME == OQ || REF_PIN_NAME == TQ}} " - "-of [get_cells -filter {{REF_NAME == OSERDESE2}}]] " - "-to [get_pins -filter {{REF_PIN_NAME == D}} " - "-of [get_cells -filter {{REF_NAME == ISERDESE2}}]]" - ) - def _eem_signal(i): n = "d{}".format(i) @@ -686,6 +689,7 @@ class _MasterBase(MiniSoC, AMPSoC): self.crg.cd_sys.clk, gtp.rxoutclk) self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq) + fix_serdes_timing_path(platform) def add_rtio(self, rtio_channels): self.submodules.rtio_moninj = rtio.MonInj(rtio_channels) @@ -806,6 +810,7 @@ class _SatelliteBase(BaseSoC): gtp.txoutclk, gtp.rxoutclk) self.submodules.rtio_clkmul = _RTIOClockMultiplier(rtio_clk_freq) + fix_serdes_timing_path(platform) def add_rtio(self, rtio_channels): self.submodules.rtio_moninj = rtio.MonInj(rtio_channels)