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gateware/amp: add kernel CPU and mailbox modules

This commit is contained in:
Sebastien Bourdeauducq 2015-04-02 16:48:59 +08:00
parent e7be00baa8
commit 5bd8d414cf
3 changed files with 78 additions and 0 deletions

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from artiq.gateware.amp.kernel_cpu import KernelCPU
from artiq.gateware.amp.mailbox import Mailbox

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from migen.fhdl.std import *
from migen.bank.description import *
from migen.bus import wishbone
from misoclib.cpu import mor1kx
from misoclib.mem.sdram.frontend.wishbone2lasmi import WB2LASMI
from misoclib.soc import mem_decoder
class KernelCPU(Module):
def __init__(self, platform, lasmim,
exec_address=0x41000000,
main_mem_origin=0x40000000,
l2_size=8192):
self._reset = CSRStorage(reset=1)
# # #
self._wb_slaves = []
# CPU core
self.clock_domains.cd_sys_kernel = ClockDomain()
self.comb += [
self.cd_sys_kernel.clk.eq(ClockSignal()),
self.cd_sys_kernel.rst.eq(self._reset.storage)
]
self.submodules.cpu = RenameClockDomains(
mor1kx.MOR1KX(platform, exec_address),
"sys_kernel")
# DRAM access
# XXX Vivado 2014.X workaround
from mibuild.xilinx.vivado import XilinxVivadoToolchain
if isinstance(platform.toolchain, XilinxVivadoToolchain):
from migen.fhdl.simplify import FullMemoryWE
self.submodules.wishbone2lasmi = FullMemoryWE(
WB2LASMI(l2_size//4, lasmim))
else:
self.submodules.wishbone2lasmi = WB2LASMI(l2_size//4, lasmim)
self.add_wb_slave(mem_decoder(main_mem_origin),
self.wishbone2lasmi.wishbone)
def get_csrs(self):
return [self._reset]
def do_finalize(self):
self.submodules.wishbonecon = wishbone.InterconnectShared(
[self.cpu.ibus, self.cpu.dbus], self._wb_slaves, register=True)
def add_wb_slave(self, address_decoder, interface):
if self.finalized:
raise FinalizeError
self._wb_slaves.append((address_decoder, interface))

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from migen.fhdl.std import *
from migen.bus import wishbone
class Mailbox(Module):
def __init__(self):
self.i1 = wishbone.Interface()
self.i2 = wishbone.Interface()
# # #
value = Signal(32)
for i in self.i1, self.i2:
self.sync += [
i.ack.eq(0),
If(i.cyc & i.stb & ~i.ack, i.ack.eq(1)),
i.dat_r.eq(value),
If(i.cyc & i.stb & i.we,
[If(i.sel[j], value[j*8:j*8+8].eq(i.dat_w[j*8:j*8+8]))
for j in range(4)]
)
]