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targets/kc705-nist_clock: add clock generator on LA32 for testing purposes

This commit is contained in:
Sebastien Bourdeauducq 2016-03-01 00:35:26 +08:00
parent a1e1f2b387
commit 5fad570f5e
4 changed files with 16 additions and 5 deletions
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6
artiq/gateware/nist_clock.py
View File

@ -48,10 +48,8 @@ fmc_adapter_io = [
Subsignal("n", Pins("LPC:CLK1_M2C_N")), Subsignal("n", Pins("LPC:CLK1_M2C_N")),
IOStandard("LVDS")), IOStandard("LVDS")),
("la32", 0, ("la32_p", 0, Pins("LPC:LA32_P"), IOStandard("LVTTL")),
Subsignal("p", Pins("LPC:LA32_P")), ("la32_n", 0, Pins("LPC:LA32_N"), IOStandard("LVTTL")),
Subsignal("n", Pins("LPC:LA32_N")),
IOStandard("LVDS")),
("spi", 0, ("spi", 0,
Subsignal("clk", Pins("LPC:LA13_N")), Subsignal("clk", Pins("LPC:LA13_N")),

4
artiq/gateware/targets/kc705.py
View File

@ -237,6 +237,10 @@ class NIST_CLOCK(_NIST_Ions):
rtio_channels.append(rtio.Channel.from_phy(phy)) rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels) self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
phy = ttl_simple.ClockGen(platform.request("la32_p"))
self.submodules += phy
rtio_channels.append(rtio.Channel.from_phy(phy))
self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels) self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
self.config["DDS_CHANNEL_COUNT"] = 11 self.config["DDS_CHANNEL_COUNT"] = 11
self.config["DDS_AD9914"] = True self.config["DDS_AD9914"] = True

2
doc/manual/core_device.rst
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@ -64,6 +64,8 @@ With the CLOCK hardware, the TTL lines are mapped as follows:
+--------------------+-----------------------+--------------+ +--------------------+-----------------------+--------------+
| 19 | LED | Output | | 19 | LED | Output |
+--------------------+-----------------------+--------------+ +--------------------+-----------------------+--------------+
| 20 | LA32_P | Clock |
+--------------------+-----------------------+--------------+
Pipistrello Pipistrello

9
examples/master/device_db.pyon
View File

@ -74,6 +74,13 @@
"class": "TTLInOut", "class": "TTLInOut",
"arguments": {"channel": 18} "arguments": {"channel": 18}
}, },
"ttl_clock_la32_p": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLClockGen",
"arguments": {"channel": 20}
},
"led": { "led": {
"type": "local", "type": "local",
@ -159,7 +166,7 @@
"loop_out": "ttl0", "loop_out": "ttl0",
"loop_in": "ttl3", "loop_in": "ttl3",
#"loop_clock_out": "TODO", "loop_clock_out": "ttl_clock_la32_p",
"loop_clock_in": "ttl7", "loop_clock_in": "ttl7",
"pmt": "ttl3", "pmt": "ttl3",