diff --git a/artiq/gateware/nist_clock.py b/artiq/gateware/nist_clock.py
index 363a339b5..3b621ac41 100644
--- a/artiq/gateware/nist_clock.py
+++ b/artiq/gateware/nist_clock.py
@@ -48,10 +48,8 @@ fmc_adapter_io = [
         Subsignal("n", Pins("LPC:CLK1_M2C_N")),
         IOStandard("LVDS")),
 
-    ("la32", 0,
-        Subsignal("p", Pins("LPC:LA32_P")),
-        Subsignal("n", Pins("LPC:LA32_N")),
-        IOStandard("LVDS")),
+    ("la32_p", 0, Pins("LPC:LA32_P"), IOStandard("LVTTL")),
+    ("la32_n", 0, Pins("LPC:LA32_N"), IOStandard("LVTTL")),
 
     ("spi", 0,
         Subsignal("clk", Pins("LPC:LA13_N")),
diff --git a/artiq/gateware/targets/kc705.py b/artiq/gateware/targets/kc705.py
index 6d2367cc4..6dd32def8 100755
--- a/artiq/gateware/targets/kc705.py
+++ b/artiq/gateware/targets/kc705.py
@@ -237,6 +237,10 @@ class NIST_CLOCK(_NIST_Ions):
         rtio_channels.append(rtio.Channel.from_phy(phy))
         self.config["RTIO_REGULAR_TTL_COUNT"] = len(rtio_channels)
 
+        phy = ttl_simple.ClockGen(platform.request("la32_p"))
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy))
+
         self.config["RTIO_DDS_CHANNEL"] = len(rtio_channels)
         self.config["DDS_CHANNEL_COUNT"] = 11
         self.config["DDS_AD9914"] = True
diff --git a/doc/manual/core_device.rst b/doc/manual/core_device.rst
index f22763151..8000a6770 100644
--- a/doc/manual/core_device.rst
+++ b/doc/manual/core_device.rst
@@ -64,6 +64,8 @@ With the CLOCK hardware, the TTL lines are mapped as follows:
 +--------------------+-----------------------+--------------+
 | 19                 | LED                   | Output       |
 +--------------------+-----------------------+--------------+
+| 20                 | LA32_P                | Clock        |
++--------------------+-----------------------+--------------+
 
 
 Pipistrello
diff --git a/examples/master/device_db.pyon b/examples/master/device_db.pyon
index da3417e9c..4dbb92ab7 100644
--- a/examples/master/device_db.pyon
+++ b/examples/master/device_db.pyon
@@ -74,6 +74,13 @@
         "class": "TTLInOut",
         "arguments": {"channel": 18}
     },
+    "ttl_clock_la32_p": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLClockGen",
+        "arguments": {"channel": 20}
+    },
+
 
     "led": {
         "type": "local",
@@ -159,7 +166,7 @@
 
     "loop_out": "ttl0",
     "loop_in": "ttl3",
-    #"loop_clock_out": "TODO",
+    "loop_clock_out": "ttl_clock_la32_p",
     "loop_clock_in": "ttl7",
 
     "pmt": "ttl3",