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phaser: 500 MHz dacclock

This commit is contained in:
Robert Jördens 2016-10-12 14:03:08 +02:00
parent 3b1d5d7eb6
commit 5f737bef76
2 changed files with 12 additions and 8 deletions
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8
artiq/examples/phaser/repository/dac_setup.py
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@ -20,9 +20,9 @@ ts = JESD204BTransportSettings(
jesd_settings = JESD204BSettings(ps, ts, did=0x5a, bid=0x5)
jesd_checksum = jesd_settings.get_configuration_checksum()
# external clk=2000MHz
# pclock=250MHz
# deviceclock_fpga=500MHz
# deviceclock_dac=2000MHz
# pclock=125MHz
# deviceclock_fpga=125MHz
# deviceclock_dac=500MHz
class DACSetup(EnvExperiment):
@ -98,7 +98,7 @@ class DACSetup(EnvExperiment):
self.ad9154.dac_write(AD9154_SPI_PAGEINDX, 0x3) # A and B dual
self.ad9154.dac_write(AD9154_INTERP_MODE, 4) # 8x
self.ad9154.dac_write(AD9154_INTERP_MODE, 1) # 2x
self.ad9154.dac_write(AD9154_MIX_MODE, 0)
self.ad9154.dac_write(AD9154_DATA_FORMAT, AD9154_BINARY_FORMAT_SET(0)) # s16
self.ad9154.dac_write(AD9154_DATAPATH_CTRL,

10
artiq/examples/phaser/startup_kernel.py
View File

@ -42,9 +42,13 @@ class StartupKernel(EnvExperiment):
self.ad9154.clock_write(AD9516_OUT5, 2*AD9516_OUT5_POWER_DOWN)
self.ad9154.clock_write(AD9516_OUT8, 1*AD9516_OUT8_POWER_DOWN)
# DAC deviceclk, clk/1
self.ad9154.clock_write(AD9516_DIVIDER_0_2, AD9516_DIVIDER_0_DIRECT_TO_OUTPUT)
self.ad9154.clock_write(AD9516_OUT1, 0*AD9516_OUT1_POWER_DOWN |
# DAC deviceclk, dclk/1
self.ad9154.clock_write(AD9516_DIVIDER_0_1, AD9516_DIVIDER_0_BYPASS)
self.ad9154.clock_write(AD9516_DIVIDER_0_2,
0*AD9516_DIVIDER_0_DIRECT_TO_OUTPUT |
0*AD9516_DIVIDER_0_DCCOFF)
self.ad9154.clock_write(AD9516_OUT1,
0*AD9516_OUT1_POWER_DOWN |
2*AD9516_OUT1_LVPECLDIFFERENTIAL_VOLTAGE)
# FPGA deviceclk, dclk/4