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examples: add Sayma VHDCI DIO

This commit is contained in:
Sebastien Bourdeauducq 2018-07-17 23:27:56 +08:00
parent 8b9a8be12a
commit 5e62910a8d
2 changed files with 86 additions and 0 deletions

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core_addr = "sayma-1.lab.m-labs.hk"
device_db = {
"core": {
"type": "local",
"module": "artiq.coredevice.core",
"class": "Core",
"arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
},
"core_log": {
"type": "controller",
"host": "::1",
"port": 1068,
"command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
},
"core_cache": {
"type": "local",
"module": "artiq.coredevice.cache",
"class": "CoreCache"
},
"core_dma": {
"type": "local",
"module": "artiq.coredevice.dma",
"class": "CoreDMA"
},
"fmcdio_dirctl_clk": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 6}
},
"fmcdio_dirctl_ser": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 7}
},
"fmcdio_dirctl_latch": {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 8}
},
"fmcdio_dirctl": {
"type": "local",
"module": "artiq.coredevice.shiftreg",
"class": "ShiftReg",
"arguments": {"clk": "fmcdio_dirctl_clk",
"ser": "fmcdio_dirctl_ser",
"latch": "fmcdio_dirctl_latch"}
},
}
for i in range(8):
device_db["ttl" + str(i)] = {
"type": "local",
"module": "artiq.coredevice.ttl",
"class": "TTLOut",
"arguments": {"channel": 9+i},
}

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from artiq.experiment import *
from artiq.coredevice.fmcdio_vhdci_eem import *
class Demo(EnvExperiment):
def build(self):
self.setattr_device("core")
self.setattr_device("fmcdio_dirctl")
self.ttls = [self.get_device("ttl" + str(i)) for i in range(8)]
self.dirctl_word = (
shiftreg_bits(2, dio_bank0_out_pins) |
shiftreg_bits(2, dio_bank1_out_pins))
@kernel
def run(self):
self.core.reset()
delay(10*ms)
self.fmcdio_dirctl.set(self.dirctl_word)
delay(10*ms)
while True:
for ttl in self.ttls:
ttl.pulse(1*ms)