From 5e62910a8d14690a8a7293414726b409ea443cc7 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Tue, 17 Jul 2018 23:27:56 +0800
Subject: [PATCH] examples: add Sayma VHDCI DIO

---
 artiq/examples/sayma_master/device_db.py      | 61 +++++++++++++++++++
 .../examples/sayma_master/repository/demo.py  | 25 ++++++++
 2 files changed, 86 insertions(+)
 create mode 100644 artiq/examples/sayma_master/device_db.py
 create mode 100644 artiq/examples/sayma_master/repository/demo.py

diff --git a/artiq/examples/sayma_master/device_db.py b/artiq/examples/sayma_master/device_db.py
new file mode 100644
index 000000000..9b6b24df3
--- /dev/null
+++ b/artiq/examples/sayma_master/device_db.py
@@ -0,0 +1,61 @@
+core_addr = "sayma-1.lab.m-labs.hk"
+
+device_db = {
+    "core": {
+        "type": "local",
+        "module": "artiq.coredevice.core",
+        "class": "Core",
+        "arguments": {"host": core_addr, "ref_period": 1/(8*150e6)}
+    },
+    "core_log": {
+        "type": "controller",
+        "host": "::1",
+        "port": 1068,
+        "command": "aqctl_corelog -p {port} --bind {bind} " + core_addr
+    },
+    "core_cache": {
+        "type": "local",
+        "module": "artiq.coredevice.cache",
+        "class": "CoreCache"
+    },
+    "core_dma": {
+        "type": "local",
+        "module": "artiq.coredevice.dma",
+        "class": "CoreDMA"
+    },
+
+    "fmcdio_dirctl_clk": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 6}
+    },
+    "fmcdio_dirctl_ser": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 7}
+    },
+    "fmcdio_dirctl_latch": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 8}
+    },
+    "fmcdio_dirctl": {
+        "type": "local",
+        "module": "artiq.coredevice.shiftreg",
+        "class": "ShiftReg",
+        "arguments": {"clk": "fmcdio_dirctl_clk",
+                      "ser": "fmcdio_dirctl_ser",
+                      "latch": "fmcdio_dirctl_latch"}
+    },
+}
+
+for i in range(8):
+    device_db["ttl" + str(i)] = {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 9+i},
+    }
diff --git a/artiq/examples/sayma_master/repository/demo.py b/artiq/examples/sayma_master/repository/demo.py
new file mode 100644
index 000000000..23add53c2
--- /dev/null
+++ b/artiq/examples/sayma_master/repository/demo.py
@@ -0,0 +1,25 @@
+from artiq.experiment import *
+from artiq.coredevice.fmcdio_vhdci_eem import *
+
+
+class Demo(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.setattr_device("fmcdio_dirctl")
+
+        self.ttls = [self.get_device("ttl" + str(i)) for i in range(8)]
+
+        self.dirctl_word = (
+            shiftreg_bits(2, dio_bank0_out_pins) |
+            shiftreg_bits(2, dio_bank1_out_pins))
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        delay(10*ms)
+        self.fmcdio_dirctl.set(self.dirctl_word)
+        delay(10*ms)
+
+        while True:
+            for ttl in self.ttls:
+                ttl.pulse(1*ms)