forked from M-Labs/artiq
drtio/transceiver/gth: fix single transceiver case
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5b0f9cc6fd
@ -205,7 +205,7 @@ class GTHSingle(Module):
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tx_reset_deglitched.attr.add("no_retiming")
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self.sync += tx_reset_deglitched.eq(~tx_init.done)
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self.clock_domains.cd_rtio_tx = ClockDomain()
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if mode == "master":
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if mode == "master" or mode == "single":
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self.specials += \
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Instance("BUFG_GT", i_I=self.txoutclk, o_O=self.cd_rtio_tx.clk, i_DIV=0)
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self.specials += AsyncResetSynchronizer(self.cd_rtio_tx, tx_reset_deglitched)
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