From 5b0f9cc6fd3aa91cd4b2eb70f3c97a38960cbf6a Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Fri, 23 Feb 2018 12:15:47 +0100 Subject: [PATCH] drtio/transceiver/gth: fix single transceiver case --- artiq/gateware/drtio/transceiver/gth_ultrascale.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/drtio/transceiver/gth_ultrascale.py b/artiq/gateware/drtio/transceiver/gth_ultrascale.py index 735bfa970..55e81ab47 100644 --- a/artiq/gateware/drtio/transceiver/gth_ultrascale.py +++ b/artiq/gateware/drtio/transceiver/gth_ultrascale.py @@ -205,7 +205,7 @@ class GTHSingle(Module): tx_reset_deglitched.attr.add("no_retiming") self.sync += tx_reset_deglitched.eq(~tx_init.done) self.clock_domains.cd_rtio_tx = ClockDomain() - if mode == "master": + if mode == "master" or mode == "single": self.specials += \ Instance("BUFG_GT", i_I=self.txoutclk, o_O=self.cd_rtio_tx.clk, i_DIV=0) self.specials += AsyncResetSynchronizer(self.cd_rtio_tx, tx_reset_deglitched)