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urukul: faster spi clock

This commit is contained in:
Robert Jördens 2018-01-22 08:13:27 +00:00
parent ca1fdaa190
commit 5a9035b122
1 changed files with 1 additions and 1 deletions
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artiq/coredevice/urukul.py
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@ -15,7 +15,7 @@ _SPIT_CFG_WR = 2
_SPIT_CFG_RD = 16 _SPIT_CFG_RD = 16
_SPIT_ATT_WR = 2 _SPIT_ATT_WR = 2
_SPIT_ATT_RD = 16 _SPIT_ATT_RD = 16
_SPIT_DDS_WR = 16 _SPIT_DDS_WR = 3
_SPIT_DDS_RD = 16 _SPIT_DDS_RD = 16
# CFG configuration register bit offsets # CFG configuration register bit offsets