forked from M-Labs/artiq
gateware: add Zotino SPI to NIST CLOCK target
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@ -3,10 +3,10 @@
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Release notes
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Release notes
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=============
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=============
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4.0
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4.0 (unreleased)
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---
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----------------
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No further notes.
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* The DDS channel number for the NIST CLOCK target has changed.
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3.0
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3.0
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@ -33,7 +33,7 @@ device_db = {
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"class": "DDSGroupAD9914",
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"class": "DDSGroupAD9914",
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"arguments": {
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"arguments": {
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"sysclk": 3e9,
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"sysclk": 3e9,
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"first_dds_bus_channel": 26,
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"first_dds_bus_channel": 29,
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"dds_bus_count": 2,
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"dds_bus_count": 2,
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"dds_channel_count": 3
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"dds_channel_count": 3
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}
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}
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@ -156,20 +156,20 @@ device_db = {
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"type": "local",
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"type": "local",
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"module": "artiq.coredevice.dds",
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"module": "artiq.coredevice.dds",
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"class": "DDSChannelAD9914",
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"class": "DDSChannelAD9914",
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"arguments": {"bus_channel": 27, "channel": 0},
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"arguments": {"bus_channel": 29, "channel": 0},
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"comment": "Comments work in DDS panel as well"
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"comment": "Comments work in DDS panel as well"
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},
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},
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"dds1": {
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"dds1": {
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"type": "local",
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"type": "local",
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"module": "artiq.coredevice.dds",
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"module": "artiq.coredevice.dds",
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"class": "DDSChannelAD9914",
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"class": "DDSChannelAD9914",
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"arguments": {"bus_channel": 27, "channel": 1}
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"arguments": {"bus_channel": 29, "channel": 1}
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},
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},
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"dds2": {
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"dds2": {
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"type": "local",
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"type": "local",
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"module": "artiq.coredevice.dds",
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"module": "artiq.coredevice.dds",
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"class": "DDSChannelAD9914",
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"class": "DDSChannelAD9914",
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"arguments": {"bus_channel": 27, "channel": 2}
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"arguments": {"bus_channel": 29, "channel": 2}
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},
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},
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"lda": {
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"lda": {
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@ -107,6 +107,27 @@ _sdcard_spi_33 = [
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)
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)
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]
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]
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_zotino = [
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("zotino_spi_p", 0,
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Subsignal("clk", Pins("HPC:LA08_P")),
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Subsignal("mosi", Pins("HPC:LA09_P")),
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Subsignal("miso", Pins("HPC:LA10_P")),
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Subsignal("cs_n", Pins("HPC:LA11_P")),
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IOStandard("LVDS_25")
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),
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("zotino_spi_n", 0,
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Subsignal("clk", Pins("HPC:LA08_N")),
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Subsignal("mosi", Pins("HPC:LA09_N")),
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Subsignal("miso", Pins("HPC:LA10_N")),
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Subsignal("cs_n", Pins("HPC:LA11_N")),
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IOStandard("LVDS_25")
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),
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("zotino_ldac", 0,
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Subsignal("p", Pins("HPC:LA13_P")),
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Subsignal("n", Pins("HPC:LA13_N")),
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IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE")
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)
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]
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class _NIST_Ions(MiniSoC, AMPSoC):
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class _NIST_Ions(MiniSoC, AMPSoC):
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mem_map = {
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mem_map = {
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@ -142,6 +163,7 @@ class _NIST_Ions(MiniSoC, AMPSoC):
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self.platform.add_extension(_sma33_io)
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self.platform.add_extension(_sma33_io)
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self.platform.add_extension(_ams101_dac)
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self.platform.add_extension(_ams101_dac)
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self.platform.add_extension(_sdcard_spi_33)
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self.platform.add_extension(_sdcard_spi_33)
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self.platform.add_extension(_zotino)
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i2c = self.platform.request("i2c")
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i2c = self.platform.request("i2c")
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda])
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@ -237,6 +259,16 @@ class NIST_CLOCK(_NIST_Ions):
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rtio_channels.append(rtio.Channel.from_phy(
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rtio_channels.append(rtio.Channel.from_phy(
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phy, ofifo_depth=4, ififo_depth=4))
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phy, ofifo_depth=4, ififo_depth=4))
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phy = spi.SPIMaster(self.platform.request("zotino_spi_p", 0),
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self.platform.request("zotino_spi_n", 0))
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4))
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pads = platform.request("zotino_ldac")
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phy = ttl_serdes_7series.Output_8X(pads.p, pads.n)
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy))
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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phy = dds.AD9914(platform.request("dds"), 11, onehot=True)
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self.submodules += phy
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self.submodules += phy
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rtio_channels.append(rtio.Channel.from_phy(phy,
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rtio_channels.append(rtio.Channel.from_phy(phy,
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@ -68,6 +68,8 @@ With the CLOCK hardware, the TTL lines are mapped as follows:
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+--------------------+-----------------------+--------------+
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+--------------------+-----------------------+--------------+
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| 21 | LA32_P | Clock |
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| 21 | LA32_P | Clock |
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+--------------------+-----------------------+--------------+
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+--------------------+-----------------------+--------------+
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| 28 | ZOTINO_LDAC | Output |
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+--------------------+-----------------------+--------------+
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The board has RTIO SPI buses mapped as follows:
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The board has RTIO SPI buses mapped as follows:
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@ -84,8 +86,10 @@ The board has RTIO SPI buses mapped as follows:
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+--------------+--------------+--------------+--------------+------------+
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+--------------+--------------+--------------+--------------+------------+
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| 26 | MMC_SPI_CS_N | MMC_SPI_MOSI | MMC_SPI_MISO | MMC_SPI_CLK|
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| 26 | MMC_SPI_CS_N | MMC_SPI_MOSI | MMC_SPI_MISO | MMC_SPI_CLK|
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+--------------+--------------+--------------+--------------+------------+
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+--------------+--------------+--------------+--------------+------------+
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| 27 | ZOTINO_CS_N | ZOTINO_MOSI | ZOTINO_MISO | ZOTINO_CLK |
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+--------------+--------------+--------------+--------------+------------+
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The DDS bus is on channel 27.
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The DDS bus is on channel 29.
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NIST QC2
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NIST QC2
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