From 5803ac9998aecd3242c35e8fbb8c43b7f7ca04c5 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Mon, 23 Oct 2017 15:04:30 +0800 Subject: [PATCH] gateware: add Zotino SPI to NIST CLOCK target --- RELEASE_NOTES.rst | 6 ++--- artiq/examples/master/device_db.py | 8 +++---- artiq/gateware/targets/kc705_dds.py | 34 ++++++++++++++++++++++++++++- doc/manual/core_device.rst | 6 ++++- 4 files changed, 45 insertions(+), 9 deletions(-) diff --git a/RELEASE_NOTES.rst b/RELEASE_NOTES.rst index 1590da53d..57caf91ca 100644 --- a/RELEASE_NOTES.rst +++ b/RELEASE_NOTES.rst @@ -3,10 +3,10 @@ Release notes ============= -4.0 ---- +4.0 (unreleased) +---------------- -No further notes. +* The DDS channel number for the NIST CLOCK target has changed. 3.0 diff --git a/artiq/examples/master/device_db.py b/artiq/examples/master/device_db.py index bbafc111c..0483a6ae0 100644 --- a/artiq/examples/master/device_db.py +++ b/artiq/examples/master/device_db.py @@ -33,7 +33,7 @@ device_db = { "class": "DDSGroupAD9914", "arguments": { "sysclk": 3e9, - "first_dds_bus_channel": 26, + "first_dds_bus_channel": 29, "dds_bus_count": 2, "dds_channel_count": 3 } @@ -156,20 +156,20 @@ device_db = { "type": "local", "module": "artiq.coredevice.dds", "class": "DDSChannelAD9914", - "arguments": {"bus_channel": 27, "channel": 0}, + "arguments": {"bus_channel": 29, "channel": 0}, "comment": "Comments work in DDS panel as well" }, "dds1": { "type": "local", "module": "artiq.coredevice.dds", "class": "DDSChannelAD9914", - "arguments": {"bus_channel": 27, "channel": 1} + "arguments": {"bus_channel": 29, "channel": 1} }, "dds2": { "type": "local", "module": "artiq.coredevice.dds", "class": "DDSChannelAD9914", - "arguments": {"bus_channel": 27, "channel": 2} + "arguments": {"bus_channel": 29, "channel": 2} }, "lda": { diff --git a/artiq/gateware/targets/kc705_dds.py b/artiq/gateware/targets/kc705_dds.py index 7aad8930b..f39703182 100755 --- a/artiq/gateware/targets/kc705_dds.py +++ b/artiq/gateware/targets/kc705_dds.py @@ -107,6 +107,27 @@ _sdcard_spi_33 = [ ) ] +_zotino = [ + ("zotino_spi_p", 0, + Subsignal("clk", Pins("HPC:LA08_P")), + Subsignal("mosi", Pins("HPC:LA09_P")), + Subsignal("miso", Pins("HPC:LA10_P")), + Subsignal("cs_n", Pins("HPC:LA11_P")), + IOStandard("LVDS_25") + ), + ("zotino_spi_n", 0, + Subsignal("clk", Pins("HPC:LA08_N")), + Subsignal("mosi", Pins("HPC:LA09_N")), + Subsignal("miso", Pins("HPC:LA10_N")), + Subsignal("cs_n", Pins("HPC:LA11_N")), + IOStandard("LVDS_25") + ), + ("zotino_ldac", 0, + Subsignal("p", Pins("HPC:LA13_P")), + Subsignal("n", Pins("HPC:LA13_N")), + IOStandard("LVDS_25"), Misc("DIFF_TERM=TRUE") + ) +] class _NIST_Ions(MiniSoC, AMPSoC): mem_map = { @@ -142,6 +163,7 @@ class _NIST_Ions(MiniSoC, AMPSoC): self.platform.add_extension(_sma33_io) self.platform.add_extension(_ams101_dac) self.platform.add_extension(_sdcard_spi_33) + self.platform.add_extension(_zotino) i2c = self.platform.request("i2c") self.submodules.i2c = gpio.GPIOTristate([i2c.scl, i2c.sda]) @@ -236,7 +258,17 @@ class NIST_CLOCK(_NIST_Ions): self.submodules += phy rtio_channels.append(rtio.Channel.from_phy( phy, ofifo_depth=4, ififo_depth=4)) - + + phy = spi.SPIMaster(self.platform.request("zotino_spi_p", 0), + self.platform.request("zotino_spi_n", 0)) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy, ififo_depth=4)) + + pads = platform.request("zotino_ldac") + phy = ttl_serdes_7series.Output_8X(pads.p, pads.n) + self.submodules += phy + rtio_channels.append(rtio.Channel.from_phy(phy)) + phy = dds.AD9914(platform.request("dds"), 11, onehot=True) self.submodules += phy rtio_channels.append(rtio.Channel.from_phy(phy, diff --git a/doc/manual/core_device.rst b/doc/manual/core_device.rst index efe153c30..544337268 100644 --- a/doc/manual/core_device.rst +++ b/doc/manual/core_device.rst @@ -68,6 +68,8 @@ With the CLOCK hardware, the TTL lines are mapped as follows: +--------------------+-----------------------+--------------+ | 21 | LA32_P | Clock | +--------------------+-----------------------+--------------+ +| 28 | ZOTINO_LDAC | Output | ++--------------------+-----------------------+--------------+ The board has RTIO SPI buses mapped as follows: @@ -84,8 +86,10 @@ The board has RTIO SPI buses mapped as follows: +--------------+--------------+--------------+--------------+------------+ | 26 | MMC_SPI_CS_N | MMC_SPI_MOSI | MMC_SPI_MISO | MMC_SPI_CLK| +--------------+--------------+--------------+--------------+------------+ +| 27 | ZOTINO_CS_N | ZOTINO_MOSI | ZOTINO_MISO | ZOTINO_CLK | ++--------------+--------------+--------------+--------------+------------+ -The DDS bus is on channel 27. +The DDS bus is on channel 29. NIST QC2