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fir: simplify latency compensation 

Don't try to tweak out the last bit of latency by feeding the HBF input
early. Instead feed it late so the interpolated samples are early and
the latency is an even multiple of the super-sample cycle.
This commit is contained in:
Robert Jördens 2017-06-28 19:13:43 +02:00
parent d1e5dd334f
commit 55b5b87490
1 changed files with 1 additions and 1 deletions
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artiq/gateware/dsp/fir.py
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@ -165,7 +165,7 @@ class ParallelHBFUpsampler(Module):
self.parallelism *= 2 self.parallelism *= 2
hbf = ParallelFIR(coeff, self.parallelism, width, **kwargs) hbf = ParallelFIR(coeff, self.parallelism, width, **kwargs)
self.submodules += hbf self.submodules += hbf
self.comb += [a.eq(b) for a, b in zip(hbf.i[::2], i)] self.comb += [a.eq(b) for a, b in zip(hbf.i[1::2], i)]
i = hbf.o i = hbf.o
self.latency += hbf.latency self.latency += hbf.latency
self.o = i self.o = i