From 55b5b8749048418fbd954addc659f4414f132af1 Mon Sep 17 00:00:00 2001 From: Robert Jordens Date: Wed, 28 Jun 2017 19:13:43 +0200 Subject: [PATCH] fir: simplify latency compensation Don't try to tweak out the last bit of latency by feeding the HBF input early. Instead feed it late so the interpolated samples are early and the latency is an even multiple of the super-sample cycle. --- artiq/gateware/dsp/fir.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/artiq/gateware/dsp/fir.py b/artiq/gateware/dsp/fir.py index 0a63ac133..2a6a462d5 100644 --- a/artiq/gateware/dsp/fir.py +++ b/artiq/gateware/dsp/fir.py @@ -165,7 +165,7 @@ class ParallelHBFUpsampler(Module): self.parallelism *= 2 hbf = ParallelFIR(coeff, self.parallelism, width, **kwargs) self.submodules += hbf - self.comb += [a.eq(b) for a, b in zip(hbf.i[::2], i)] + self.comb += [a.eq(b) for a, b in zip(hbf.i[1::2], i)] i = hbf.o self.latency += hbf.latency self.o = i